Datasheet

SRC4392

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SBFS029D –DECEMBER 2005–REVISED DECEMBER 2012

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

0 0 0 LOL RXAMLL RXCKOD1 RXCKOD0 RXCKOE

RXCKOE RXCKOE Output Enable

This bit is used to enable or disable the recovered clock output, RXCKO (pin 12). When disabled,

the output is set to a high-impedance state.

RXCKOE RXCKO Output State

0 Disabled; the RXCKO output is set to high-impedance. (Default)

1 Enabled; the recovered master clock is available at RXCKO.

RXCKOD

RXCKO Output Clock Divider

[1:0]

These bits are utilized to set the clock divider at the output of PLL2. The output of the divider is

the RXCKO clock, available internally or at the RXCKO output (pin 12).

RXCKOD1 RXCKOD0 RXCKO Output Divider

0 0 Passthrough, no division is performed. (Default)

0 1 Divide the PLL2 clock output by 2.

1 0 Divide the PLL2 clock output by 4.

1 1 Divide the PLL2 clock output by 8.

RXAMLL Receiver Automatic Mute for Loss of Lock

This bit is used to set the automatic mute function for the DIR block when a loss of lock is

indicated by both the AES3 decoder and PLL2.

RXAMLL Receiver Auto-Mute Function

0 Disabled (Default)

1 Enabled; audio data output from the DIR block is forced low for a loss of

lock condition.

LOL Receiver Loss of Lock Mode for the Recovered Clock (output from PLL2)

This bit is used to set the mode of operation for PLL2 when a loss of lock condition occurs.

LOL Receiver PLL2 Operation

0 The PLL2 output clock is stopped for a loss of lock condition. (Default)

1 The PLL2 output clock free runs when a loss of lock condition occurs.

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

P3 P2 P1 P0 J5 J4 J3 J2

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

J1 J0 D13 D12 D11 D10 D9 D8

Product Folder Links: SRC4392