Datasheet

SRC4392

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SBFS029D –DECEMBER 2005–REVISED DECEMBER 2012

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

0 0 RATIO READY 0 0 TSLIP TBTI

TBTI Transmitter Buffer Transfer Status, Active High

When DIT User Access (UA) to Transmitter Access (TA) buffer transfers are enabled (the

TXBTD bit in control register 0x08 is set to 0), and the TBTI interrupt is unmasked (the MTBTI

bit in control register 0x0B is set to 1), the TBTI bit will be set to 1 when the UA-to-TA buffer

transfer has completed. This configuration also causes the INT output (pin 23) to be driven low

and the TX bit in status register 0x02 to be set to 1, indicating that an interrupt has occurred.

TSLIP Transmitter Source Data Slip Status, Active High

The TSLIP bit will be set to 1 when either an asynchronous data slip or block start condition is

detected, and the TSLIP interrupt is unmasked (the MTSLIP bit in control register 0x0B is set

to 1). The BSSL bit in control register 0x07 is used to set the source for this interrupt.

The TSLIP bit being forced to 1 will also cause the INT output (pin 23) to be driven low and the

TX bit in status register 0x02 to be set to 1, indicating that an interrupt has occurred.

READY SRC Rate Estimator Ready Status, Active High

The READY bit will be set to 1 when the input and output rate estimators have completed the

Fast mode portion of the rate estimation process, and the READY interrupt is unmasked (the

MREADY bit in control register 0x0B is set to 1). This will also cause the INT output (pin 23) to

be driven low and the SRC bit in status register 0x02 to be set to 1, indicating that an interrupt

has occurred.

RATIO SRC Ratio Status, Active High

The RATIO bit will be set to 1 when the input sampling rate is higher than the output sampling

rate, and the RATIO interrupt is unmasked (the MRATIO bit in control register 0x0B is set to

1). This will also cause the INT output (pin 23) to be driven low and the SRC bit in status

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