Datasheet

SRC4392
SBFS029D DECEMBER 2005REVISED DECEMBER 2012
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Register 09: Transmitter Control Register 3
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 0 0 0 0 VALSEL TXCUS1 TXCUS0
TXCUS[1:0] Transmitter Channel Status and User Data Source
These bits select the source of the channel status (or C) data and user (or U) data which is used
to load the DIT User Access (UA) buffers.
TXCUS1 TXCUS0 DIT UA Buffer Source
0 0 The buffers will not be updated. (Default)
1 The buffers are updated via the SPI or I
2
C host
0
interface.
1 0 The buffers are updated via the DIR RA buffers.
The first 10 bytes of the buffers are updated via the SPI
1 1 or I
2
C host, while the remainder of the buffers are
updated via the DIR RA buffers.
VALSEL Transmitter Validity Bit Source
This bit is utilized to select the source for the validity (or V) bit in the AES3-encoded output data
stream.
VALSEL Validity (or V) Bit Source Selection
0 The VALID bit in control register 0x07.
1 The V bit is transferred from the DIR block with zero latency.
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