Datasheet

SRC4392

SBFS029D –DECEMBER 2005–REVISED DECEMBER 2012

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BLSM Transmitter Block Start Input/Output Mode

This bit is used to select the input/output mode for the DIT block start pin, BLS (pin 35).

BLSM BLS Pin Mode

0 Input (Default)

1 Output

TXIS[1:0] Transmitter Input Data Source

These bits are used to select the audio data source for the DIT function block.

TXIS1 TXIS0 Output Word Length

0 0 Port A (Default)

0 1 Port B

1 0 DIR

1 1 SRC

TXDIV[1:0] Transmitter Master Clock Divider

These bits are used to select the Transmitter master clock divider, which determines the output

frame rate.

TXDIV1 TXDIV0 Clock Divider

0 0 Divide the master clock by 128. (Default)

0 1 Divide the master clock by 256.

1 0 Divide the master clock by 384.

1 1 Divide the master clock by 512.

TXCLK Transmitter Master Clock Source

This bit is used to select the master clock source for the Transmitter block.

TXCLK Transmitter Master Clock Source

0 MCLK Input (Default)

1 RXCKO; the recovered master clock from the DIR function block.

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)

BYPMUX1 BYPMUX0 AESMUX LDMUX TXBTD AESOFF TXMUTE TXOFF

TXOFF Transmitter Line Driver Output Enable

This bit is used to enable or disable the TX+ (pin 32) and TX– (pin 31) line driver outputs.

TXOFF Transmitter Line Driver

0 Enabled; the line driver outputs function normally. (Default)

1 Disabled; the line driver outputs are forced low.

TXMUTE Transmitter Audio Data Mute

This bit is used to set the 24 bits of audio and auxiliary data to all zeros for both Channels 1 and

TXMUTE Transmitter Audio Data Mute

0 Disabled (Default)

1 Enabled; the audio data for both Channels 1 and 2 are set to all zeros.

Product Folder Links: SRC4392