Datasheet

SRC4392
www.ti.com SBFS029D –DECEMBER 2005–REVISED DECEMBER 2012
Register 04: Port A Control Register 2
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 0 0 0 ACLK1 ACLK0 ADIV1 ADIV0
ADIV[1:0] Port A Master Clock Divider
These bits are used to set the master clock divider for generating the LRCKA clock for Port A
when configured for Master mode operation. BCKA is always set to 64 times the LRCKA clock
rate in Master mode.
ADIV1 ADIV0 Master Mode Clock Divider
0 0 Divide By 128 (Default)
0 1 Divide By 256
1 0 Divide By 384
1 1 Divide By 512
ACLK[1:0] Port A Master Clock Source
These bits are used to set the master clock source for Port A when configured for Master mode
operation.
ACLK1 ACLK0 Master Clock Source
0 0 MCLK (Default)
0 1 RXCKI
1 0 RXCKO
1 1 Reserved
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