Datasheet
BCKB
RX1+
RX2+
RX2-
RX3+
VCC
AGND
LOCK
RXCKO
SYNC
BLS
AESOUT
VDD33
TX+
TX-
DGND2
GPO2
GPO1
MCLK
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
RXCKI
11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31
LRCKB
DGND1
SDINB
VDD18
SDOUTB
CPM
BGND
CS
/A0
DGND3
CCLK/SCL
VIO
CDIN/A1
SDOUTA
CDOUT/SDA
SDINA
INT
LRCKA
RST
BCKA
RX1-
36
35
34
33
32
31
30
29
28
27
26
25
SYNC
BLS
AESOUT
VDD33
TX+
TX-
DGND2
GPO4
GPO3
GPO2
GPO1
MCLK
BCKB
LRCKB
SDINB
SDOUTB
BGND
DGND3
VIO
NC
SDOUTA
SDINA
LRCKA
BCKA
RXCKI
MUTE
RDY
DGND1
VDD18
CPM
CS
CCLK
CDIN
CDOUT
INT
RST
1
2
3
4
5
6
7
8
9
10
11
12
RX1+
RX1-
RX2+
RX2-
RX3+
RX3-
RX4+
RX4-
VCC
AGND
LOCK
RXCKO
48 47 46 45 44 43 42
41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
NC = No Connection
SRC4392
SBFS029D –DECEMBER 2005–REVISED DECEMBER 2012
www.ti.com
PFB PACKAGE
TQFP-48
RKP PACKAGE
(Top View)
QFN-40
(Top View)
NC = No connection.
PIN DESCRIPTIONS
PIN NO.
NAME PFB RKP I/O DESCRIPTION
AESOUT 34 28 Output DIT buffered AES3-encoded data
AGND 10 8 Ground DIR comparator and PLL power-supply ground
BCKA 37 31 I/O Audio serial Port A bit clock
BCKB 48 1 I/O Audio serial Port B bit clock
Substrate ground, connect to AGND (pin 10 for PFB package, pin 8 for
BGND 44 37 Ground
RKP package)
BLS 35 29 I/O DIT block start clock
CCLK or SCL 20 16 Input
Serial data clock for SPI mode or I
2
C mode
CDIN orA1 21 17 Input
SPI port serial data input or programmable slave address for I
2
C mode
CDOUT or SDA 22 18 I/O
SPI port serial data output (3-state output) or serial data I/O for I
2
C
mode
Control port mode
CPM 18 14 Input
(0 = SPI mode, 1 = I
2
C mode)
CS or A0 19 15 Input Chip select (active low) for SPI mode or programmable slave address
for I
2
C mode
DGND1 16 12 Ground Digital core ground
DGND2 30 24 Ground DIR line receiver bias and DIT line driver digital ground
DGND3 43 36 Ground Logic I/O ground
GPO1 26 22 Output General-purpose output 1
GPO2 27 23 Output General-purpose output 2
GPO3 28 — Output General-purpose output 3
GPO4 29 — Output General-purpose output 4
INT 23 19 Output Interrupt flag (open-drain, active low)
LOCK 11 9 Output DIR PLL lock flag (active low)
10 Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated
Product Folder Links: SRC4392