Datasheet
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SRC4382
SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007
These bits are utilized to enable or disable the digital de-emphasis filter manually. The de-emphasis filter is intended to process 50/15 μ s
pre-emphasized audio material at the following input sampling rates:
DEM1 DEM0 De-Emphasis Filter Function
0 0 De-Emphasis Disabled (Default)
0 1 De-Emphasis Enabled for f
S
= 48kHz
1 0 De-Emphasis Enabled for f
S
= 44.1kHz
1 1 De-Emphasis Enabled for f
S
= 32kHz
Note: When the AUTODEM bit is set to 1, the setting of the DEM0 and DEM1 bits are ignored.
AUTODEM Automatic De-Emphasis Configuration
This bit enables or disables the automatic de-emphasis function, which monitors the channel status bits from the DIR function block and
determines whether de-emphasis is enabled and for which sampling frequency. This function is valid for only 50/15 μ s pre-emphasized data
and one of the three supported sampling rates (32kHz, 44.1kHz, or 48kHz).
AUTODEM Automatic De-Emphasis Function
0 Disabled (Default)
1 Enabled
Register 2F: SRC Control Register 3
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
OWL1 OWL0 0 0 0 0 0 0
OWL[1:0] SRC Output Word Length
These bits select the word length for the SRC output data. The word length reduction is performed by utilizing triangular PDF dithering.
OWL1 OWL0 SRC Output Word Length
0 0 24 Bits (Default)
0 1 20 Bits
1 0 18 Bits
1 1 16 Bits
Note: When the SRC is selected as the output data source for Port A or B and the data format for the port is set to Right-Justified, the
proper word length must be selected in the Port A or B control registers such that it matches the corresponding SRC output data word
length set by the OWL0 and OWL1 bits.
Register 30: SRC Control Register 4
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
These bits are utilized to configure the SRC digital output attenuation for the Left Channel when the TRACK bit in register 0x2D is set to 0. The attenuation
setting for the Left channel also applies to the Right channel when TRACK bit in register 0x2D is set to 1.
Output Attenuation (dB) = – N נ 0.5, where N = AL[7:0]
DEC
.
Register 31: SRC Control Register 5
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
These bits are utilized to configure the SRC digital output attenuation for the Right Channel when the TRACK bit in register 0x2D is set to 0.
Output Attenuation (dB) = – N נ 0.5, where N = AR[7:0]
DEC
.
Register 32: SRC Ratio Readback Register (Read-Only)
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
SRI4 SRI3 SRI2 SRI1 SRI0 SRF10 SRF9 SRF8
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