Datasheet

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SRC4382
SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007
RATIO SRC Ratio Status, Active High
The RATIO bit will be set to 1 when the input sampling rate is higher than the output sampling rate, and the RATIO interrupt is
unmasked (the MRATIO bit in control register 0x0B is set to 1). This will also cause the INT output (pin 23) to be driven low and the
SRC bit in status register 0x02 to be set to 1, indicating that an interrupt has occurred.
Register 0B: SRC and DIT Interrupt Mask Register
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 0 MRATIO MREADY 0 0 MTSLIP MTBTI
MBTI Transmitter Buffer Transfer Interrupt Mask
MTBI BTI Interrupt Mask
0 BTI interrupt is masked. (Default)
1 BTI interrupt is enabled.
MTSLIP Transmitter TSLIP Interrupt Mask
MTSLIP TSLIP Interrupt Mask
0 TSLIP interrupt is masked. (Default)
1 TSLIP interrupt is enabled.
MREADY SRC Ready Interrupt Mask
MREADY READY Interrupt Mask
0 READY interrupt is masked. (Default)
1 READY interrupt is enabled.
MRATIO SRC Ratio Interrupt Mask
MRATIO RATIO Interrupt Mask
0 RATIO interrupt is masked. (Default)
1 RATIO interrupt is enabled.
Register 0C: SRC and DIT Interrupt Mode Register
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
RATIOM1 RATIOM0 READYM1 READYM0 TSLIPM1 TSLIPM0 TBTIM1 TBTIM0
TBTIM[1:0] Transmitter Buffer Transfer Interrupt Mode
These bits are utilized to select the active trigger state for the BTI interrupt.
TBTIM1 TBTIM0 Interrupt Active State
0 0 Rising Edge Active (Default)
0 1 Falling Edge Active
1 0 Level Active
1 1 Reserved
TSLIPM[1:0] Transmitter Data Source Slip Interrupt Mode
These bits are utilized to select the active trigger state for the TSLIP interrupt.
TSLIPM1 TSLIPM0 Interrupt Active State
0 0 Rising Edge Active (Default)
0 1 Falling Edge Active
1 0 Level Active
1 1 Reserved
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