Datasheet
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SRC4382
SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007
LDMUX Transmitter Line Driver Input Source Selection
This bit is used to select the input source for the DIT differential line driver outputs.
LDMUX Line Driver Input Source
0 DIT AES3 Encoder Output (Default)
1 Bypass Multiplexer Output
AESMUX AESOUT CMOS Buffer Input Source Selection
This bit is used to select the input source for the AESOUT CMOS logic level output.
AESMUX AESOUT Buffer Input Source
0 DIT AES3 Encoder Output (Default)
1 Bypass Multiplexer Output
BYPMUX[1:0] Bypass Multiplexer Source Selection
These bits select the line receiver output to be utilized as the Bypass multiplexer data source.
BYPMUX1 BYPMUX0 Line Receiver Output Selection
0 0 RX1 (Default)
0 1 RX2
1 0 RX3
1 1 RX4
Register 09: Transmitter Control Register 3
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 0 0 0 0 VALSEL TXCUS1 TXCUS0
TXCUS[1:0] Transmitter Channel Status and User Data Source
These bits select the source of the channel status (or C) data and user (or U) data which is used to load the DIT User Access (UA) buffers.
TXCUS1 TXCUS0 DIT UA Buffer Source
0 0 The buffers will not be updated. (Default)
1
0
The buffers are updated via the SPI or I
2
C host interface.
1 0 The buffers are updated via the DIR RA buffers.
The first 10 bytes of the buffers are updated via the SPI or I
2
C host, while the
1 1
remainder of the buffers are updated via the DIR RA buffers.
VALSEL Transmitter Validity Bit Source
This bit is utilized to select the source for the validity (or V) bit in the AES3-encoded output data stream.
VALSEL Validity (or V) Bit Source Selection
0 The VALID bit in control register 0x07.
1 The V bit is transferred from the DIR block with zero latency.
Register 0A: SRC and DIT Status (Read-Only)
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
0 0 RATIO READY 0 0 TSLIP TBTI
TBTI Transmitter Buffer Transfer Status, Active High
When DIT User Access (UA) to Transmitter Access (TA) buffer transfers are enabled (the TXBTD bit in control register 0x08 is set to
0), and the TBTI interrupt is unmasked (the MTBTI bit in control register 0x0B is set to 1), the TBTI bit will be set to 1 when the
UA-to-TA buffer transfer has completed. This configuration also causes the INT output (pin 23) to be driven low and the TX bit in status
register 0x02 to be set to 1, indicating that an interrupt has occurred.
TSLIP Transmitter Source Data Slip Status, Active High
The TSLIP bit will be set to 1 when either an asynchronous data slip or block start condition is detected, and the TSLIP interrupt is
unmasked (the MTSLIP bit in control register 0x0B is set to 1). The BSSL bit in control register 0x07 is used to set the source for this
interrupt.
The TSLIP bit being forced to 1 will also cause the INT output (pin 23) to be driven low and the TX bit in status register 0x02 to be set
to 1, indicating that an interrupt has occurred.
READY SRC Rate Estimator Ready Status, Active High
The READY bit will be set to 1 when the input and output rate estimators have completed the Fast mode portion of the rate estimation
process, and the READY interrupt is unmasked (the MREADY bit in control register 0x0B is set to 1). This will also cause the INT
output (pin 23) to be driven low and the SRC bit in status register 0x02 to be set to 1, indicating that an interrupt has occurred.
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