Datasheet

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MCLK
RXCKO
UserAccess
(UA)Buffers
TransmitterAccess
(TA)Buffers
Channel
Status
User
Data
FromReceiver
Access(RA) Buffer
FromReceiver
Access(RA) Buffer
To/From SPIorI C
2
HostInterface
To/From SPIorI C
2
HostInterface
PortA
PortB
DIR
SRC
TXCLK
TXCUS[1:0] TXBTD
TXIS[1:0]
BLS(pin35)
SYNC(pin36)
AE 3S
Encoder
AESMUX
LDMUX
AESOFF
TXOFF
From
Bypass
Multiplexer
Output
TX+(pin32)
TX (pin31)-
AESOUT
(pin34)
Master
Clock
Source
Daat
Source
Channel
Status
User
Daat
TXMUTE BL MS
TXDIV[1:0]
SRC4382
SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007
The AES3 encoder output is connected to the output line driver and CMOS buffer source multiplexers. As shown
in Figure 65 , the source multiplexers allow the line driver or buffer to be driven by the AES3-encoded data from
the DIT, or by the bypass multiplexer, which is associated with the outputs of the four differential input line
receivers preceding the DIR core. The bypass multiplexer allows for one of the four line receiver outputs to be
routed to the line driver or buffer output, thereby providing a bypass mode of operation. Both the line driver and
CMOS output buffer include output disables, set by the TXOFF and AESOFF bits in control register 0x08. When
the outputs are disabled, they are forced to a low logic state.
The AES3 encoder includes an output mute function that sets all bits for both the Channel 1 and 2 audio and
auxiliary data to zero. The preamble, V, U, and C bits are unaffected, while the P bit is recalculated. The mute
function is controlled using the TXMUTE bit in control register 0x08.
Figure 65. Digital Interface Transmitter (DIT) Functional Block Diagram
The AES3 encoder includes a block start input/output pin, BLS (pin 35). The BLS pin may be programmed as an
input or output. The input/output state of the BLS pin is programmed using the BLSM bit in control register 0x07.
By default, the BLS pin is configured as an input.
As an input, the BLS pin may be utilized to force a block start condition, whereby the start of a new block of
channel status and user data is initiated by generating a Z preamble for the next frame of data. The BLS input
must be synchronized with the DIT internal SYNC clock. This clock is output on SYNC (pin 36). The SYNC clock
rising edge is aligned with the start of each frame for the AES3-encoded data output by the DIT. Figure 66
illustrates the format required for an external block start signal, as well as indicating the format when the BLS pin
is configured as an output. When the BLS pin is an output, the DIT generates the block start signal based upon
the internal SYNC clock.
For details regarding DIT control and status registers, as well as channel status and user data buffers, refer to
the Control Registers and Channel Status and User Data Buffer Maps sections.
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