Datasheet

Reference Clock Generation
3-10
3.5 Reference Clock Generation
The SRC4194EVM supports a flexible configuration for the SRC4194 refer-
ence clock generation. Figure 3−4 illustrates the PLL and clock connections
used for the reference clocks.
Both SRC A and SRC B have their own reference clocks, referred to as RCKIA
and RCKIB, respectively. The reference clocks may be derived by onboard
PLL clock generators (U25 and U28), or by external clock sources applied at
connectors J12 and J13. Table 3−6 summarizes the output rates available
from the onboard PLL circuits.
The reference clocks are also used by the transmitter sections of the EVM, and
are made available at the audio input and output ports for use by external hard-
ware.
Figure 3−4. Reference Clock Generation, Connections, and Configuration
Switch SW10
A_PLL
LO = Use PLL (U25)
HI = Use Ext Clock (J12)
Switch SW10
A_FS1
A_FS2
A_SR
SCKO2
To RCKIA
SRC A EXT
CLOCK (J12)
FS1 FS2 SR
U25
PLL1705DBQ
Switch SW10
B_PLL
LO = Use PLL (U28)
HI = Use Ext Clock (J13)
Switch SW10
B_CLK
LO = Use PLL or EXT CLK
HI = Use RCKIA
Switch SW10
B_FS1
B_FS2
B_SR
SCKO2
SRC B EXT
CLOCK (J13)
FS1 FS2 SR
U28
PLL1705DBQ
To RCK IB
Table 3−6.PLL Configuration for U25 and U28
x_SR (switch SW10) x_FS2 (switch SW10) x_FS1 (switch SW10) PLL Output Rate
LO LO LO 12.288 MHz
LO LO HI 11.2896 MHz
LO HI LO 8.192 MHz
LO HI HI Reserved
HI LO LO 24.576 MHz
HI LO HI 22.5792 MHz
HI HI LO 16.384 MHz
HI HI HI Reserved
Where x = A or B Where x = A or B Where x = A or B