Datasheet
SRC4192, SRC4193
SBFS022B
26
www.ti.com
Figure 13 shows the interface between the SRC4192 or
SRC4193 output port and the DIT4096 or DIT4192 audio
serial port. Once again, the V
IO
supplies for both the
SRC4192/4193 and DIT4096/4192 are set to +3.3V for
compatibility.
SRC4192, SRC4193
LRCKO
BCKO
SDOUT
RCKI
SYNC
SCLK
SDATA
DIT4096, DIT4192
MCLK
Clock
Select
Assumes V
IO
= +3.3V for SRC4192, SRC4293 and DIT4096, DIT4192
REF Clock
Generator
DIT Clock
Generator
TX+
TX–
AES3, S/PDIF
OUTPUT
Like the SRC4192 or SRC4193 output port, the DIT4096 and
DIT4192 audio serial port may be configured as a Master or
Slave. In cases where the SRC4192/4193 output port is set
to Master mode, it is recommended to use the reference
clock source (RCKI) as the master clock source (MCLK) for
the DIT4096/4192, to ensure that the transmitter is synchro-
nized to the SRC4192/4193 output port data.
TDM APPLICATIONS
The SRC4192 and SRC4193 support a TDM output mode,
which allows multiple devices to be daisy-chained together
to create a serial frame. Each device occupies one sub-
frame within a frame, and each sub-frame carries two chan-
nels (Left followed by Right). Each sub-frame is 64 bits long,
with 32 bits allotted for each channel. The audio data for
each channel is left justified within the allotted 32 bits. Figure
14 illustrates the TDM frame format, while Figure 15 shows
TDM input timing parameters, which are listed in the Electri-
cal Characteristics table of this data sheet.
LRCKO
BCKO
SDOUT
N = Number of Daisy-Chained Devices
One Sub-Frame contains 64 bits, with 32 bits per channel.
For each channel, the audio data is left justified, MSB first format, with the word length determined by the OWL[1:0] pins/bits.
Left Right
Sub-Frame 1 Sub-Frame 2 Sub-Frame N
One Frame = 1/f
s
Left Right Left Right
t
LROS
t
TDMS
t
LROH
t
TDMH
LRCKO
BCKO
TDMI
FIGURE 15. Input Timing for TDM Mode.
FIGURE 14. TDM Frame Format.
FIGURE 13. Interfacing the SRC4193 to the DIT4096/4192
Digital Audio Interface Transmitter.