Datasheet
SRC4192, SRC4193
SBFS022B
24
www.ti.com
APPLICATIONS INFORMATION
This section of the data sheet provides practical applications
information for hardware and systems engineers who will be
designing the SRC4192 and SRC4193 into their end equip-
ment.
RECOMMENDED CIRCUIT CONFIGURATION
Typical connection diagrams for the SRC4192 and SRC4193
are shown in Figures 10 and 11, respectively. Recom-
mended values for power supply bypass capacitors are
included. These capacitors should be placed as close to the
IC package as possible.
LGRP
RCKI
NC
SDIN
BCKI
LRCKI
VIO
DGND
BYPAS
IFMT0
IFMT1
IFMT2
RST
MUTE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SRC4192
Audio Input
Device
Reference
Clock
From/To
Control
Logic
V
DD
= +3.3V
10µF
MODE2
MODE1
MODE0
BCKO
LRCKO
SDOUT
V
DD
DGND
TDMI
OFMT0
OFMT1
OWL0
OWL1
RDY
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Audio Output
Device
0.1µF
To Pin 22
To Pin 21
V
IO
= +1.65V to V
DD
0.1µF10µF
To Pin 7
To Pin 8
From
Control
Logic
Register 4: Digital Attenuation Register – Left Channel
Register defaults to 00
HEX
, or 0dB (unity gain).
Output Attenuation (dB) = (–N x 0.5), where N = AL[7:0]
DEC
Register 5: Digital Attenuation Register – Right Channel
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
Register defaults to 00
HEX
, or 0dB (unity gain).
Output Attenuation (dB) = (–N x 0.5), where N = AR[7:0]
DEC
When the TRACK bit in Control Register 1 is set to 1, the Left Channel attenuation setting will be used for the Right Channel
attenuation.
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
FIGURE 10. Typical Connection Diagram for the SRC4192.