Datasheet

Selecting the DIT4192 Master Clock Source and Frequency
3-9
Setup Guide
When the EXT DIT CLK input at connector J7 is selected as the master clock
source, the device will support an external +3.3V CMOS logic level clock
source with frequencies up to 25MHz.
In addition to DIT4192 master clock source selection, the DIT4192 master
clock divider must be selected using the CLK0 and CLK1 elements of switch
SW3. The master clock source frequency will be divided by the factor listed in
Table 3–8 to determine the transmitter output frame rate, as well as the SYNC
and SCLK clock rate when the DIT4192 is configured in Master mode.
Table 3–8.PLL Master Clock Selection for the DIT4192
CLK1 CLK0 DIT4192 MCLK Divider
LO LO Divide by 128
LO HI Divide by 256
HI LO Divide by 384
HI
HI Divide by 512