Datasheet

Selecting the DIT4192 Master Clock Source and Frequency

3-8

3.7 Selecting the DIT4192 Master Clock Source and Frequency

The OM/~S element of switch SW9 and the ~TPLL element of SW6 are used

to select the master clock source for the DIT4192 digital audio transmitter. The

master clock (or MCLK) frequency determines the output frame (or sampling)

rate of the transmitter, in addition to determining the SYNC and SCLK output

rates when the DIT4192 is configured in Master mode. Table 3–6 summarizes

the DIT4192 master clock source options.

When OM/~S is set to HI (that is, the SRC419x output port is the Master and

the DIT4192 is a Slave), the reference clock source for the SRC419x will also

be used as the master clock source for the DIT4192. This ensures synchro-

nization between the SRC419x output port and DIT4192 audio serial port.

Table 3–6.DIT4192 Master Clock Selection

~TPLL OM/~S DIT4192 MCLK Source

LO LO PLL1705 (U6)

HI LO EXT DIT CLK (J7)

HI SRC419x Ref Clock

X = Don’t Care

When OM/~S is set to LO (that is, the SRC419x output port is a Slave and the

DIT4192 is the Master), the ~TPLL element of switch SW6 is utilized to select

the DIT4192 master clock source, as shown in Table 3–6.

When the PLL1705 (U6) is selected as the master clock source, the TSR,

TFS1, and TFS2 elements of switch SW6 are utilized to select the PLL output

rate. Table 3–7 summarizes the PLL output rate options.

Table 3–7.PLL Master Clock Source Selection for the DIT4192

TSR TFS2 TFS1 PLL Output Rate (MHz)

LO LO LO 12.288

LO LO HI 11.2896

LO HI LO 8.192

LO HI HI Reserved

HI LO LO 24.576

HI LO HI 22.5792

HI HI LO 16.384

HI HI Reserved