Datasheet

Selecting the SRC419x Reference Clock Source and Frequency
3-7
Setup Guide
3.6 Selecting the SRC419x Reference Clock Source and Frequency
The ~PLL element of switch SW9 is used to select the reference clock source
for the SRC419x. The reference clock input is utilized by the SRC419x rate es-
timator, as well as the input or output port when configured in Master mode.
The Master mode port derives the LRCK and BCK clock outputs from the refer-
ence clock input.
When ~PLL is set to LO, the PLL1705 (U16) is selected as the reference clock
source for the SRC419x. Table 3–5 summarizes the output rate selections for
the PLL1705.
When ~PLL is set to HI, the EXT SRC CLK input (J6) is selected as the refer-
ence clock input. The EXT SRC CLK input supports +3.3V CMOS external
clock sources with frequencies up to 50MHz.
Table 3–5.PLL Reference Clock Selection for the SRC419x
SSR SFS2 SFS1 PLL Output Rate (MHz)
LO LO LO 12.288
LO LO HI 11.2896
LO HI LO 8.192
LO HI HI Reserved
HI LO LO 24.576
HI LO HI 22.5792
HI HI LO 16.384
HI
HI HI Reserved