User’s Guide June 2003 SBAU088
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the specified input and output ranges described in the EVM User’s Guide. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Contents Preface About This Manual This document provides the information needed to setup and operate the SRC4192EVM evaluation module. For a more detailed description of the SRC4190, SRC4192, or SRC4193 products, please refer to the product data sheets available from the Texas Instruments web site at http://www.ti.com. Support documents are listed in the sections of this guide entitled Related Documentation from Texas Instruments and Additional Documentation.
Contents This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. Related Documentation From Texas Instruments The following documents provide information regarding Texas Instruments integrated circuits used in the assembly of the SRC4192EVM. These documents are available from the TI web site.
Contents Additional Documentation The following documents provide information regarding selected non–TI components, which are used in the assembly of the SRC4192EVM. These documents are available from the corresponding manufacturers. Document Manufacturer CS8414 Data Sheet HCM49 Series Crystals SC937–02 Data Sheet Cirrus Logic, http://www.cirrus.com Citizen, http://www.citizencrystal.com Scientific Conversion http://www.scientificonversion.com Scientific Conversion http://www.scientificonversion.
Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 The SRC4190, SRC4192, and SRC4193 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 EVM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 EVM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Figure 1–1. Functional Block Diagram for the SRC4192 and SRC4193 . . . . . . . . . . . . . . . . . . . . . . Figure 1–2. Functional Block Diagram for the SRC4192EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4–1. SRC4192EVM Schematic Diagram (page 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4–2. SRC4192EVM Schematic Diagram (page 2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4–3. PCB Silkscreen, Top Layer .
Contents Electrostatic Discharge Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 This chapter provides a brief technical overview for the SRC4190, SRC4192, and SRC4193 asynchronous sample rate converters, as well as a general description and feature list for the SRC4192EVM. Topic Page 1.1 The SRC4190, SRC4192 and SRC4193 . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 EVM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 EVM Features . . . . . . . . . . . . . . . . . . . . . . . . . . .
The SRC4190, SRC4192, and SRC4193 1.1 The SRC4190, SRC4192, and SRC4193 The SRC4192 and SRC4193 are stereo asynchronous sample rate converters designed for professional and broadcast audio applications. Operation at input and output sampling frequencies up to 212kHz is supported, with an input/output sampling ratio range of 16:1 to 1:16. Excellent dynamic range and THD+N are achieved by employing high performance, linear phase digital filtering with better than 140dB of image rejection.
The SRC4190, SRC4192, and SRC4193 Figure 1–1.
The SRC4190, SRC4192, and SRC4193 1.3 EVM Features Key features for the SRC4192EVM include: - Zero Insertion Force (ZIF) socket for easily interchanging SRC4190, SRC4192 and SRC4193 devices. The Analog Devices AD1895 and AD1896 are also supported for head–to–head testing. - On–board or external clock generation. - On–board receiver and transmitter supports AES3 input and output (75 Ω BNC connections provided). - Buffered audio input and output ports using standard dual in–line headers.
Introduction 1-5
Chapter 2 This chapter provides information regarding SRC4192EVM handling and unpacking, absolute operating conditions, and a description of the factory default switch and jumper configuration. Topic Page 2.1 Electrostatic Discharge Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Absolute Maximum Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 Unpacking the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Operating Conditions 2.1 Electrostatic Discharge Warning Many of the components on the SRC4192EVM are susceptible to damage by electrostatic discharge (ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation. Caution: Failure to observe ESD handling procedures may result in damage to EVM components. 2.
Default Configuration 2.4 Default Configuration The factory default switch and jumper settings are shown in Table 2, and result in the following EVM configuration: - The SRC4192 Input Port is set to Slave mode, with the CS8414 receiver selected as the input source. - The SRC4192 Output Port is set to Slave mode, with the DIT4192 trans- mitter selected as the output device. - The SRC PLL (U16) is selected as the SRC419x reference clock source and is set to 24.576MHz.
Chapter 3 This chapter provides a step–by–step guide to configuring the SRC4192EVM for device evaluation. Follow the sections to walk through the setup of the SRC4192EVM. Topic Page 3.1 Power Supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 Selecting the Input & Output Port Modes . . . . . . . . . . . . . . . . . . . . . .
Power Supply Configuration 3.1 Power Supply Configuration The SRC4192EVM requires a single +5 volt regulated dc power supply, connected at the +5V terminal of J9. The GND terminal of J9 should be connected to the power supply ground or common terminal. The supply should not be connected to terminal block J9 while hot, as damage may occur to the EVM. At no time should the power supply exceed the absolute maximum rating. 3.
Selecting the Input & Output Port Modes 3.3 Selecting the Input & Output Port Modes The input and output ports of the SRC419x devices support seven modes of operation. Table 3–1 summarizes the mode settings for the SRC419x devices. In Master mode, the LRCK and BCK clocks are outputs, derived from the reference clock (RCKI) input. In Slave mode, the LRCK and BCK clocks are inputs, which are generated by the audio input or output device.
Selecting the Input & Output Data Formats 3.4 Selecting the Input & Output Data Formats The SRC419x devices support a flexible set of audio data formats. Table 3–2 summarizes the input and output format options for the sample rate converters. Section 3.5 of this chapter describes the format configuration for the digital audio receiver and transmitter devices. When ~4193 is set to HI, the IFMT0, IFMT1 and IFMT2 elements of switch SW7 are used to select the input port data format.
Selecting an Input Source and an Output Port 3.5 Selecting an Input Source and an Output Port The ~IPORT element of switch SW9 is utilized to select the input source. When ~IPORT is set to LO, the buffered Audio Input Port at connector J1 is selected as the input source. This port is designed to interface to devices that support Left Justified, Right Justified, and I2S formatted digital audio data.
Selecting an Input Source and an Output Port When ~PORT = HI, the output of the DIT4192 digital audio transmitter (U5) at connector J4 is selected as the output port. This port is designed to interface to digital audio signal analyzers and devices that accept AES3 formatted digital audio data. This includes the S/PDIF inputs of A/V receivers and digital recording devices.
Selecting the SRC419x Reference Clock Source and Frequency 3.6 Selecting the SRC419x Reference Clock Source and Frequency The ~PLL element of switch SW9 is used to select the reference clock source for the SRC419x. The reference clock input is utilized by the SRC419x rate estimator, as well as the input or output port when configured in Master mode. The Master mode port derives the LRCK and BCK clock outputs from the reference clock input.
Selecting the DIT4192 Master Clock Source and Frequency 3.7 Selecting the DIT4192 Master Clock Source and Frequency The OM/~S element of switch SW9 and the ~TPLL element of SW6 are used to select the master clock source for the DIT4192 digital audio transmitter. The master clock (or MCLK) frequency determines the output frame (or sampling) rate of the transmitter, in addition to determining the SYNC and SCLK output rates when the DIT4192 is configured in Master mode.
Selecting the DIT4192 Master Clock Source and Frequency When the EXT DIT CLK input at connector J7 is selected as the master clock source, the device will support an external +3.3V CMOS logic level clock source with frequencies up to 25MHz. In addition to DIT4192 master clock source selection, the DIT4192 master clock divider must be selected using the CLK0 and CLK1 elements of switch SW3.
Miscellaneous Functions 3.8 Miscellaneous Functions This section provides information regarding several SRC419x and DIT4192 functions not described previously in this chapter. Low group delay operation is controlled using the LGRP element of switch SW7, or by the LGRP bit in Control Register 2 when using the SRC4193. The low group delay option reduces the overall latency of the interpolation filter by 32/fsIN, where fsIN is the input sampling rate in hertz (Hz).
Miscellaneous Functions The Mute function is controlled using the MUTE element of switch SW7, or by the MUTE bit of Control Register 1 when using the SRC4193. This function employs a soft mute technique, which provides for artifact–free muting of the SRC419x output port. Table 3–11 summarizes Mute function operation. Table 3–11. Mute Function Configuration MUTE Soft Mute Function LO Disabled HI Enabled A Direct Down–Sampling option is available only when using the SRC4193.
Reset Functions 3.9 Reset Functions The SRC4192EVM includes three reset switches, one each for the SRC419x (SW8), the CS8414 receiver (SW2), and the DIT4192 transmitter (SW4). Each switch is a momentary contact, normally open push–button with 10kΩ pull–up resistors to the +3.3V supply. To reset a device, momentarily press, then release, the corresponding reset switch. This allows the user to reset the devices at will, if necessary or desired.
Chapter 4 ! " # This chapter provides the electrical and physical layout information for the SRC4192EVM. The bill of materials is included for component and manufacturer reference. The schematic diagram is shown, beginning on page 4-2. The printed circuit board layouts are shown on pages 4-4 through 4-6. The bill of materials is shown starting on page 4-7. Topic Page 4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic 4.1 Schematic The complete electrical schematics of for the SRC4192EVM are shown in Figure 4–1 and Figure 4–2. Figure 4–1.
Schematic Figure 4–2.
Component Layout 4.2 Component Layout The printed circuit board plots for the SRC4192EVM are shown in Figure 4–3 through Figure 4–5. The PCB is a two–layer board, with most components mounted on the top (or component) side. The power supply bypass capacitors for U15 are mounted on the bottom (or solder) side of the PCB. Figure 4–3.
Component Layout Figure 4–4.
Component Layout Figure 4–5.
SRC4192EVM 470 16 R24, R25 R22, R23 (continued on next page) 150 15 R15—R17 R1—R14 13 75 LED1 12 14 JMP1 11 47.5 J9 C44 10 22µF 6 C37—C43 J8 4.7µF 5 C1—C36 9 0.1µF 4 C53, C54 J1, J3, J5 0.01µF 3 C52 J2, J4, J6, J7 68000 pF 2 C45–C48 8 18pF 1 Reference Designator 7 Value Item Table 4–1. Bill of Materials 4.
4-8 SRC4192EVM SW2, SW4, SW8 T1 T2 U1 U2 U3 U4 U5 U6, U16 U7, U14 U8, U13 U9, U18, U21 U10, U17, U20 U11, U19 U12 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 (continued on next page) SW7, SW9, SW10 RN5—RN7 21 10K 19 RN1, RN2, RN4 SW1, SW3, SW6 10K 18 R18—R21 Reference Designator 20 10K Value 17 Item 1 2 3 3 2 2 2 1 1 1 1 1 1 1 3 3 3 3 3 4 Qty Per Bd Table 4–1.
U22 U23 X1, X2 38 39 40 41 42 43 Reference Designator U15 (DUT) Value 37 Item 1 2 1 4 2 1 1 Qty Per Bd Table 4–1. Bill of Materials (continued) Texas Instruments Citizen Enplas–Tesco 3M Bumpon Samtec Texas Instruments Texas Instruments Manufacturer SN74AHC244PW HCM49–27.000MABJT OTS–28(34)–0.65–01 SJ–5003 SNT–100–BK–G–H REG1117–3.
