Datasheet

SRC4190
SBFS023B
20
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INTERFACING TO DIGITAL AUDIO RECEIVERS
AND TRANSMITTERS
The SRC4190 input and output ports are designed to inter-
face to a variety of audio devices, including receivers
and transmitters commonly used for AES/EBU,
S/PDIF, and CP1201 communications.
Texas Instruments manufactures the DIR1703 digital audio
interface receiver and DIT4096/4192 digital audio transmit-
ters to address these applications.
Figure 9 illustrates interfacing the DIR1703 to the SRC4190
input port. The DIR1703 operates from a single +3.3V sup-
ply, which requires the V
IO
supply (pin 7) for the SRC4190 to
be set to +3.3V for interface compatibility.
Like the SRC4190 output port, the DIT4096 and DIT4192
audio serial port may be configured as a Master or Slave. In
cases where the SRC4190 output port is set to Master mode,
it is recommended to use the reference clock source (RCKI)
as the master clock source (MCLK) for the DIT4096/4192, to
ensure that the transmitter is synchronized to the SRC4190
output port data.
TDM APPLICATIONS
The SRC4190 supports a TDM output mode, which allows
multiple devices to be daisy-chained together to create a
serial frame. Each device occupies one sub-frame within a
frame, and each sub-frame carries two channels (Left fol-
lowed by Right). Each sub-frame is 64 bits long, with 32 bits
allotted for each channel. The audio data for each channel is
Left Justified within the allotted 32 bits. Figure 11 illustrates
the TDM frame format, while Figure 12 shows the TDM input
timing parameters, which are listed in the Electrical Charac-
teristics table of this data sheet.
DIR1703
LRCKO
BCKO
DATA
SCKO
LRCKI
BCKI
SDIN
SRC4190
RCLI
Clock
Select
Assumes V
IO
= +3.3V for SRC4190
Clock
Generator
RCV DIN
AES3, S/PDIF
Input
FIGURE 9. Interfacing the SRC4190 to the DIR1703 Digital
Audio Interface Receiver.
Figure 10 shows the interface between the SRC4190 output
port and the DIT4096 or DIT4192 audio serial port.
Once again, the V
IO
supplies for both the SRC4190 and
DIT4096/4192 are set to +3.3V for compatibility.
SRC4190
LRCKO
BCKO
SDOUT
RCKI
SYNC
SCLK
SDATA
DIT4096, DIT4192
MCLK
Clock
Select
Assumes V
IO
= +3.3V for SRC4190 and DIT4096, DIT4192
REF Clock
Generator
DIT Clock
Generator
TX+
TX–
AES3, S/PDIF
OUTPUT
FIGURE 10. Interfacing the SRC4190 to the DIT4096/4192
Digital Audio Interface Transmitter.
LRCKO
BCKO
SDOUT
N = Number of Daisy-Chained Devices
One Sub-Frame contains 64 bits, with 32 bits per channel.
For each channel, the audio data is Left Justified, MSB first format, with the word length determined by the OWL[1:0] pins/bits.
Left Right
Sub-Frame 1 Sub-Frame 2 Sub-Frame N
One Frame = 1/f
s
Left Right Left Right
FIGURE 11. TDM Frame Format.