Datasheet

SRC4190
SBFS023B
17
www.ti.com
t
LRIS
t
SIH
t
LDIS
t
SIL
t
LDIH
LRCKI
BCKI
SDIN
Left Channel
(a) Left Justified Data Format
(b) Right Justified Data Format
Right Channel
LRCKO
BCKI
SDIN
MSB LSB LSBMSB
LRCKI
BCKI
SDIN
MSB MSB LSBLSB
(c) I
2
S Data Format
1/f
S
LRCKI
BCKI
SDIN
MSB LSB MSB LSB
FIGURE 4. Input Data Formats.
FIGURE 5. Input Port Timing.
The left/right word clock, LRCKI (pin 6), may be configured
as an input or output pin. In Slave mode, LRCKI is an input
pin, while in Master mode LRCKI is an output pin. In either
case, the clock rate is equal to f
S
, the input sampling
frequency. The LRCKI duty cycle is fixed to 50% for Master
mode operation.
Table 2 illustrates data format selection for the input port.
The IFMT0 (pin 10), IFMT1 (pin 11), and IFMT2 (pin 12)
inputs are utilized to set the input port data format.
IFMT2 IFMT1 IFMT0 INPUT PORT DATA FORMAT
0 0 0 24-Bit Left Justified
0 0 1 24-Bit I
2
S
0 1 0 Unused
0 1 1 Unused
1 0 0 16-Bit Right Justified
1 0 1 18-Bit Right Justified
1 1 0 20-Bit Right Justified
1 1 1 24-Bit Right Justified
TABLE 2. Input Port Data Format Selection.