Datasheet

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SBFS026B − JUNE 2004 − REVISED SEPTEMBER 2007
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34
SDOUTA
BCKOA
LRCKOA
TDMIA
BCKIA
LRCKIA
SDINA
DGND
V
IO
IFMTA0
IFMTA1
IFMTA2
OFMTA0
OFMTA1
OWLA0
OWLA1
BYPA
LGRPA0
LGRPA1
DDNA
DEMA0
DEMA1
MODEA0
MODEA1
MODEA2
RATIOA
RDYA
MUTEA
RCKIA
RST
H/S
DGND
VDD33
VDD33
REGEN
64
63
62
61
60
59
58
57
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SRC4184
SDOUTB
BCKOB
LRCKOB
TDMIB
BCKIB
LRCKIB
SDINB
IFMTB0
IFMTB1
IFMTB2
OFMTB0
OFMTB1
OWLB0
OWLB1
BYPB
LGRPB0
LGRPB1
DDNB
DEMB0
CDOUT
CS
CCLK
CDIN
RATIOB
RDYB
MUTEB
RCKIB
VDD18
VDD18
49
50
51
52
53
54
55
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
Digital
Audio I/O
(DIR, DIT, DSP)
Host Processor
with SPI Port
and GPIO
Digital
Audio I/O
(DIR, DIT, DSP)
V
IO
Supply
0.1
µ
F10
µ
F
From Reference Source Clock
RefertoFigure12
Refer to Figure 12
From Reference Clock Source
From System or External Reset or Host Processor
To/From Host Processor
+
Figure 11. Typical Pin Connections for Software Mode Operation
SRC4184
VDD33
VDD33
DGND
VDD18
VDD18
REGEN
24
25
23
27
28
26
+
+
0.1µF
10
µ
F
0.1µF
10µF
+1.8V
+3.3V
Install jumper JMP1 and associated bypass capacitors
only if +3.3V will be used as the core voltage.
Install jumper JMP2 and associated bypass capacitors
only if +1.8V will be used as the core voltage.
Drive Low when using a +1.8V core supply at the VDD18 pins.
Drive High when using a +3.3V core supply at the VDD33 pin
in order to enable the on−chip +1.8V linear voltage regulator.
Figure 12. Core Power-Supply Connection Options