Datasheet

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SBFS026B − JUNE 2004 − REVISED SEPTEMBER 2007
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33
APPLICATIONS INFORMATION
This section provides practical applications information for
hardware and systems engineers who will be designing
the SRC4184 into their end equipment.
TYPICAL CONNECTIONS
Figure 10 and Figure 11 illustrate typical connection
diagrams for Hardware and Software modes, respectively.
In Hardware mode, dedicated pins are controlled using
external logic circuitry, hardwiring pins high or low, or by
using the general-purpose I/O pins of a microprocessor or
DSP. In Software mode, the SRC4194 is controlled via the
4-wire SPI port and optional GPIO from either a
microprocessor or DSP.
Figure 12 illustrates the power-supply options for the
SRC4194. When utilizing +3.3V for the core supply, the
REGEN input (pin 26) must be driven high in order to
enable the on-chip linear voltage regulator. The VDD33
pins are supplied with +3.3V and the VDD18 pins are left
unconnected.
Recommended power supply bypass capacitor values are
shown in Figure 10 through Figure 12. Ceramic capacitors
(X7R chip type) are recommended for the 0.1µF
capacitors, while the 10µF capacitors may be tantalum or
multi-layer X7R ceramic chip type, or through-hole or
surface mount aluminum electrolytic capacitors.
When utilizing +1.8V for the core supply, the REGEN input
(pin 26) must be driven low in order to disable the on-chip
linear voltage regulator. The VDD18 pins are supplied with
+1.8V and the VDD33 pins are left unconnected.
SDOUTA
BCKOA
LRCKOA
TDMIA
BCKIA
LRCKIA
SDINA
DGND
V
IO
IFMTA0
IFMTA1
IFMTA2
OFMTA0
OFMTA1
OWLA0
OWLA1
BYPA
LGRPA0
LGRPA1
DDNA
DEMA0
DEMA1
MODEA0
MODEA1
MODEA2
RATIOA
RDYA
MUTEA
RCKIA
RST
H/S
DGND
VDD33
VDD33
REGEN
64
63
62
61
60
59
58
57
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SRC4184
SDOUTB
BCKOB
LRCKOB
TDMIB
BCKIB
LRCKIB
SDINB
IFMTB0
IFMTB1
IFMTB2
OFMTB0
OFMTB1
OWLB0
OWLB1
BYPB
LGRPB0
LGRPB1
DDNB
DEMB0
DEMB1
MODEB0
MODEB1
MODEB2
RATIOB
RDYB
MUTEB
RCKIB
VDD18
VDD18
49
50
51
52
53
54
55
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
Digital
Audio I/O
(DIR, DIT, DSP)
Control Logic,
µ
P, o r
Hardwired I/O
Digital
Audio I/O
(DIR, DIT, DSP)
Control Logic,
µ
P, o r
Hardwired I/O
V
IO
Supply
0.1
µ
F10
µ
F
From Reference Source Clock
RefertoFigure12
Refer to Figure 12
From Reference Clock Source
From System or External Reset
+
Figure 10. Typical Pin Connections for Hardware Mode Operation