Datasheet

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SBFS026B − JUNE 2004 − REVISED SEPTEMBER 2007
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32
Register 4. Digital Output Attenuation Register—Left Channel
D7
(MSB)
D6 D5 D4 D3 D2 D1
D0
(LSB)
AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
This register is utilized to program the digital output attenuation for the Left output channel of the
corresponding SRC section.
Register defaults to 00h, or 0dB (unity gain).
Output Attenuation (dB) = −N × 0.5, where N = AL[7:0]
DEC
Register 5. Digital Output Attenuation Register—Right Channel
D7
(MSB)
D6 D5 D4 D3 D2 D1
D0
(LSB)
AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
This register is utilized to program the digital output attenuation for the Right output channel of the
corresponding SRC section. When the TRACK bit in Control Register 1 is set to 1, the Left Channel
attenuation setting will also be used to set the Right Channel attenuation.
Register defaults to 00h, or 0dB (unity gain).
Output Attenuation (dB) = −N × 0.5, where N = AR[7:0]
DEC
Register 6. Sampling Ratio (read only)
D7
(MSB)
D6 D5 D4 D3 D2 D1
D0
(LSB)
SRI4 SRI3 SRI2 SRI1 SRI0 SRF10 SRF9 SRF8
Register 7. Sampling Ratio (read only)
D7
(MSB)
D6 D5 D4 D3 D2 D1
D0
(LSB)
SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRF0
The contents of Register 6 and Register 7 indicate the input-to-output sampling ratio, and can be used to
determine either the input or output sampling rates when one of the two rates is known.
Bits SRI[4:0] comprise the integer portion of the input-to-output sampling ratio.
Bits SRF[10:0] comprise the fractional portion of the input-to-output sampling ratio.
The contents of Register 6 and Register 7 are updated when Register 6 is read. Register 6 must always be
read first in order to obtain the latest ratio data for both registers.