Datasheet

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SBFS026B − JUNE 2004 − REVISED SEPTEMBER 2007

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CONTROL REGISTER DEFINITIONS

(Software Mode Only)

This section contains descriptions for each control and status register available in Software mode. Reset defaults are also

shown for each register bit.

(MSB)

D6 D5 D4 D3 D2 D1

(LSB)

PDN TRACK 0 MUTE BYPASS MODE2 MODE1 MODE0

MODE[2:0] Audio Serial Port Mode

These bits are used to select the Slave or Master mode status of the input and output serial ports.

MODE2 MODE1 MODE0 AUDIO SERIAL PORT MODE

0 0 0 Both Serial Ports are in Slave Mode (default)

0 0 1 Output Serial Port is Master with RCKI = 128f

0 1 0 Output Serial Port is Master with RCKI = 512f

0 1 1 Output Serial Port is Master with RCKI = 256f

1 0 0 Both Serial Ports are in Slave Mode

1 0 1 Input Serial Port is Master with RCKI = 128f

1 1 0 Input Serial Port is Master with RCKI = 512f

1 1 1 Input Serial Port is Master with RCKI = 256f

BYPASS Bypass Mode

This bit is logically OR’d with the bypass input (BYPA or BYPB) for the corresponding SRC section.

BYPASS FUNCTION

0 Bypass Mode disabled with normal ASRC operation. (default)

1 Bypass Mode enabled with data routed directly from the input port to the output port, bypass-

ing the ARSC function.

MUTE Output Soft Mute

This bit is logically OR’d with the MUTE input (MUTEA or MUTEB) for the corresponding SRC section.

MUTE OUTPUT MUTE FUNCTION

0 Soft mute disabled. (default)

1 Soft mute enabled with output data attenuated to all 0s

TRACK Digital Attenuation Tracking

TRACK ATTENUATION TRACKING

0 Tracking Off: Attenuation for the Left and Right channels is controlled independently by Con-

trol Register 4 and Control Register 5. (default)

1 Tracking On: Left channel attenuation setting is used for both channels.

PDN Power-Down

Setting this bit to 0 will force the corresponding SRC section into Soft Power-Down mode. All other register

settings are preserved and the SPI port remains active. Setting this bit to 1 will power-up the corresponding

SRC section using the current register settings.

This bit defaults to 0 on power-up or reset. It must be programmed to 1 by the user in order to enable normal

operation for the corresponding SRC section.