Datasheet

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SBFS026B − JUNE 2004 − REVISED SEPTEMBER 2007
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Figure 8 illustrates the protocol for register write and read
operations via the SPI port. Figure 9 shows the critical
timing parameters for the SPI port interface, which are
listed in the Electrical Characteristics table.
Byte 0 indicates the register bank, register address, and
read/write status for the operation. The functions
contained within this byte are clearly shown in Figure 8. It
should be noted that either one or both of the SRC A and
SRC B register banks may be written to in the same
operation, but only one bank can be selected at any time
for a read operation. Byte 1 is a don’t care byte. This byte
is included in the protocol in order to maintain compatibility
with current and future Texas Instruments’ digital audio
interface products, including the DIT4096, DIT4192, and
SRC4193. Bytes 0 and 1 are followed by register data
bytes.
As shown in Figure 8, a write or read operation starts by
bringing the CS
input low. Bytes 0, 1, and 2 are then written
to write or read a single register. Byte 2 is not needed for
reading registers, so the CDIN pin can be forced low after
Byte 0 for a read operation. Bringing the CS
input high after
the third byte will write or read a single register address.
However, if CS remains low after writing or reading the first
control or status byte, the port will automatically increment
the address by 1, allowing successive addresses to be
written or read sequentially. The address is automatically
incremented by 1 after each byte is written or read, as long
as the CS
input remains low. This is referred to as
Auto-Increment operation, and is always enabled for the
SPI port.
Set CS = 1 here to write/read one register location.
Keep CS = 0 to enable the auto−increment mode.
Byte 0
Hi−Z
Byte 1
Hi−Z
Byte 2
Data for A[2:0]
Byte 3
Data for A[2:0] + 1
Byte N
Data for A[2:0] + N
CS
CDIN
CDOUT
CCLK
Byte 0:
Byte 1: Don’t Care
Byte 2 through Byte N: Register Data
Byte Definition:
Header Register Data
Register Data
RWB 0 0 SB SA A2 A1 A0
MSB LSB
Set to 0.
Set to 0 for Write; set to 1 for Read.
Register
Bank Select
Register
Address
SB
0
0
1
1
SA
0
1
0
1
Write Access
Disabled
SRC A
SRC B
SRC A and B
Read Access
Disabled
SRC A
SRC B
SRC B
Figure 8. SPI Protocol for the SRC4184
CSB
CCLK
CDIN
CDOUT
Hi−Z Hi−Z
t
CSCR
t
CFCS
t
CDS
t
CFDO
t
CSZ
t
CDH
Figure 9. SPI Port Timing