Datasheet

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SBFS026B − JUNE 2004 − REVISED SEPTEMBER 2007
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23
Left Channel
(a) Left−Justified Data Format
(b) Right−Justified Data Format
Right Channel
LRCKI
BCKI
SDIN
MSB LSB LSBMSB
LRCKI
BCKI
SDIN
MSB MSB LSBLSB
(c) I
2
SDataFormat
1/f
S
LRCKI
BCKI
SDIN
MSB LSB MSB LSB
Figure 4. Input Data Formats
t
LRIS
t
SIH
t
LDIS
t
SIL
t
LDIH
LRCKI
BCKI
SDIN
Figure 5. Input Port Timing
Table 2 illustrates the data format selection for the input
port. For Hardware mode, the IFMTA0 (pin 1), IFMTA1
(pin 2), and IFMTA2 (pin 3) inputs are utilized to set the
input port data format for SRC A. IFMTB0 (pin 48), IFMTB1
(pin 47), and IFMTB2 (pin 46) are utilized to set the input
port data format for SRC B.
Table 2. Input Port Data Format Selection (x = A or B)
IFMTx2 IFMTx1 IFMTx0 INPUT PORT DATA FORMAT
0 0 0 24-Bit Left-Justified
0 0 1 24-Bit I
2
S
0 1 0 Unused
0 1 1 Unused
1 0 0 16-Bit Right-Justified
1 0 1 18-Bit Right-Justified
1 1 0 20-Bit Right-Justified
1 1 1 24-Bit Right-Justified
In Software mode, the IFMT[2:0] bits in Control Register 3
are used to select the data format for the SRC A and
SRC B register banks. The default format is 24-Bit
Left-Justified.