Datasheet

National Semiconductor Page 5 www.national.com
1.4 Component Description
The following table describes both the on-board connectors and the main components used in the SPIO-4
System shown in Figure 1.
Component 1.4.1.1 Description
J1 Serial Debug connector
J2 Header to provide access to the FPGA’s JTAG interface for debug
J3 Jumper to select J4 IO voltage (3.3V or programmable)
J4 (DBG) Debug/Development Connector(See section 2.6).
J6 (GPSI-32) GPSI-16/32 Connector to DUT.
J7 (micro_SD) This holds the microSD card for storage or development purposes
J8 (USB) USB cable Connection.
J9 (JTAG) Atmel Processor JTAG Debug Header.
J10 (POWER) +5-6V Power Supply Connection –Optional (See Section Error! Reference
source not found.).
J14 (USNAP) Additional header providing power and serial interface to processor
JP1 Jumpers for test purposes only.
U1 Atmel SAM3U Processor
U4 8Mx16 PSRAM
U5 Xilinx Spartan LX16 FPGA
D1-D4 FPGA Status LEDs (See section 2.4)
D6 1.8V PSRAM Core voltage Surface mount power LED.
D7 3.3V DUT supply voltage Surface mount power LED.
D8 5.0V DUT supply voltage Surface mount power LED.
D10 USB input power LED.
D11 1.2V FPGA Core voltage Surface mount power LED.
SW1 Reset switch
SW2 Power On pushbutton
Table 1 - Main component reference designators
1.5 SPIO-4 Board Test Points
The following table describes the main Test Points available.
Test point Description
TP1, TP3, TP16, TP18(GND) Ground test points.
TP11 3.3V Digital IO Voltage for SPIO Board
TP12 1.2V for FPGA core voltage
TP13 1.8V for PSRAM core voltage
TP14 3.3V for DUT Digital Supply
TP15 5.0V for DUT Analog Supply
Table 2 - Test Points