Datasheet

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DUT INPUT LEVEL SHIFTERS
DUT OUTPUT LEVEL SHIFTERS
RSTUFF OPTIONS TO SUPPORT CPU ONLY
CAPABILITY (NO FPGA)
DUT_VDDIO
REF_CLKA
SDRDYN_A
SCS1N_A_R
SCLK_A_R
SCS0N_A_R
SMOSI_A_R
SCS2N_A_R
DUTCS2N_A
SCS0N_A
SCLK_A
DUT_SDA
DUT_VDDIO
SMISO_A
DUT_SCL
SMOSI_A
SDRDYN_A
REF_CLKA
SCS0N_B
SCLK_B
SMISO_B
SMOSI_B
SCS1N_B
SCS2N_B
SCS3N_B
SDRDYN_B
SCS2N_B
SCS3N_B
SDRDYN_B
SCS1N_B
SCS0N_B
SCLK_B
SMISO_B
SMOSI_B
DUTCLKIN_R
DUTMISO_A_R
SCS1N_A
SCLK_A
SCS0N_A
SMOSI_A
SCS2N_A
DUTDRDYN_R
DUTSCLK_A
DUTCLKIN
DUTMISO_A
DUT_SDA
DUT_SCL
CPUMISO_A_R
SMISO_A
SCS2N_A
SCS1N_A
DUT_PWR_EN
DUT_PWR_EN
5VDUT_FLTERD
DUTMOSI_A
DUTCS0N_A
DUTCS1N_A
3p3V
3p3V
DGND
DGND
DGND
DGND
DGND
3p3V
DGND
3p3V_DUT
DGND
DGND
3p3V
3p3V_DUT
DGND
DGND
DGND
DGND
5p0V_DUT
DUTCLKIN 3
DUT_SDA3
DUT_PWR_EN3
DUT_SCL 3
CPU_CS1N_A 3
DUTDRDYN_A
3
CPUMISO_A 3
CPU_SCLK_A 3
CPU_CS0N_A 3
CPU_MOSI_A 3
DUT_PRSNT_N 3
CPU_CS2N_A 3
DUT_VDDIO11
Title
Size Document Number Rev
Date: Sheet
of
2.0
SPIO4 FPGA GPSI32 Intrfc
B
712Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet
of
2.0
SPIO4 FPGA GPSI32 Intrfc
B
712Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet
of
2.0
SPIO4 FPGA GPSI32 Intrfc
B
712Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
U5-1
XC6SLX9CSG324
U5-1
XC6SLX9CSG324
IO_L33N_0
A8
IO_L39N_0
A11
IO_L41N_0
A12
IO_L37N_GCLK12_0
A10
IO_L35N_GCLK16_0
A9
IO_L62N_VREF_0
A14
IO_L64N_SCP4_0
A15
IO_L66N_SCP0_0
A16
IO_L4N_0
A3
IO_L6N_0
A5
IO_L8N_VREF_0
A6
IO_L5N_0
A4
IO_L10N_0
A7
IO_L1P_HSWAPEN_0
D4
IO_L1N_VREF_0
C4
IO_L2P_0
B2
IO_L2N_0
A2
IO_L3P_0
D6
IO_L3N_0
C6
IO_L4P_0
B3
IO_L5P_0
B4
IO_L6P_0
C5
IO_L10P_0
C7
IO_L8P_0
B6
IO_L11P_0
D8
IO_L11N_0
C8
IO_L33P_0
B8
IO_L34P_GCLK19_0
D9
IO_L34N_GCLK18_0
C9
IO_L35P_GCLK17_0
B9
IO_L36P_GCLK15_0
D11
IO_L36N_GCLK14_0
C11
IO_L37P_GCLK13_0
C10
IO_L38P_0
G9
IO_L38N_VREF_0
F9
IO_L39P_0
B11
IO_L41P_0
B12
IO_L62P_0
B14
IO_L63P_SCP7_0
F13
IO_L63N_SCP6_0
E13
IO_L64P_SCP5_0
C15
IO_L65P_SCP3_0
D14
IO_L65N_SCP2_0
C14
IO_L66P_SCP1_0
B16
VCCO_0
B10
VCCO_0
B15
VCCO_0
B5
VCCO_0
D13
VCCO_0
D7
VCCO_0
E10
R53 0RR53 0R
R17 33RR17 33R
C99
0.1uF
C99
0.1uF
C66
0.1uF
C66
0.1uF
C64
0.1uF
C64
0.1uF
R55 0RR55 0R
R57
0R
R57
0R
C108
0.1uF
C108
0.1uF
U8
SN74LVC2T45SSOP
U8
SN74LVC2T45SSOP
VCCA
1
A1
2
A2
3
GND
4
DIRA2B
5
B2
6
B1
7
VCCB
8
C67
1.0uF
C67
1.0uF
C69
0.1uF
C69
0.1uF
R79 1.5KR79 1.5K
C73
10uF
C73
10uF
R20 33RR20 33R
R80 1.5KR80 1.5K
C105
0.1uF
C105
0.1uF
R18 33RR18 33R
R16 33RR16 33R
R13 33RR13 33R
C46
0.1uF
C46
0.1uF
C104
0.1uF
C104
0.1uF
R54
DNS
R54
DNS
J6
32PIN_FEM_HDR_RA
J6
32PIN_FEM_HDR_RA
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
U7
SN74LVC2T45SSOP
U7
SN74LVC2T45SSOP
VCCA
1
A1
2
A2
3
GND
4
DIRA2B
5
B2
6
B1
7
VCCB
8
R59
0R
R59
0R
R58
0R
R58
0R
C70
0.1uF
C70
0.1uF
C98
0.1uF
C98
0.1uF
U10
SN74LVC2T45SSOP
U10
SN74LVC2T45SSOP
VCCA
1
A1
2
A2
3
GND
4
DIRA2B
5
B2
6
B1
7
VCCB
8
C103
0.47uF
C103
0.47uF
C106
1.0uF
C106
1.0uF
C65
0.1uF
C65
0.1uF
R15 33RR15 33R
C68
0.1uF
C68
0.1uF
R56
0R
R56
0R
C71
0.1uF
C71
0.1uF
U6
SN74LVC2T45SSOP
U6
SN74LVC2T45SSOP
VCCA
1
A1
2
A2
3
GND
4
DIRA2B
5
B2
6
B1
7
VCCB
8
C72
0.1uF
C72
0.1uF
C109
1.0uF
C109
1.0uF
R14 33RR14 33R
R19 33RR19 33R
U9
SN74LVC2T45SSOP
U9
SN74LVC2T45SSOP
VCCA
1
A1
2
A2
3
GND
4
DIRA2B
5
B2
6
B1
7
VCCB
8