Datasheet

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
REQUIRED SIGNALS TO CONFIG FPGA
RDWR_B T5
VIA SERIAL OR BYTE WIDE (SELECTMAP)
CSI_B T13
CCLK R15
DO_DIN R13
D1 T14
D2 V14
D3 U5
D4 V5
D5 R3
D6 T3
D7 R5
INIT U3
M0 T15
M1 N12
RSTUFF OPTIONS TO SUPPORT
SERIAL AND PARALLEL FPGA CONFIG
NOTE:D0-7 SWAPPED GOING INTO CONFIG BITS
D2
D1
D0
D4
FPGA_CFG_CSN
D6
D5
D11
D8
D10
D15
D12
D9
D13
D14
A1
A23
A4
A14
A3
A8
A5
A2
A15
A6
A10
A12
A16
A7
A13
A9
A11
A19
A18
A17
A22
A21
A20
NBS1
NBS0
NWAIT
NCS0
NRD
A1
A17
A21
A16
A20
A14
A15
A19
A18
A22
A23
D0
D1
D2
D3
D7
D4
D6
D5
D11
D8
D9
D15
D12
D9
D13
D14
A13
A5
A9
A4
A8
A2
A11
A3
A7
A6
A12
A10
FPGA_CCLK
FPGA_CFG_CSN
DATA_D7_CFG_D0
FPGA_CCLK
D7
DATA_D7_CFG_D0
DATA_D7_CFG_D0
D3
DGND
3p3V
DGND
3p3V
3p3V
NWE3,4
FPGA_INIT_N3
FPGA_M13
FPGA_M03
NRD3,4
NCS03,4
NBS13,4
NBS03,4
NWAIT3,4
D[15:0]
3,4
A[23:1]
3,4
SCC_TD3
NCS33
SCC_TF3
CLK_12MHZ2
PCK13
PCK3
SCC_CLK3
NCS23
Title
Size Document Number Rev
Date: Sheet
of
2.0
SPIO4 FPGA SRAM & Configuration Intrfc
B
512Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet
of
2.0
SPIO4 FPGA SRAM & Configuration Intrfc
B
512Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
Title
Size Document Number Rev
Date: Sheet
of
2.0
SPIO4 FPGA SRAM & Configuration Intrfc
B
512Wednesday, November 17, 2010
870600474-001
National Semiconductor, Santa Clara, CA 95052
2010 National Semiconductor
R73
DNS
R73
DNS
R75
DNS
R75
DNS
R77
DNS
R77
DNS
C43
0.1uF
C43
0.1uF
C44
0.1uF
C44
0.1uF
C45
10uF
C45
10uF
R74
0R
R74
0R
R76
0R
R76
0R
R78
0R
R78
0R
U5-2
XC6SLX9CSG324
U5-2
XC6SLX9CSG324
IO_L44N_A2_M1DQ7_1
J18
IO_L45N_A0_M1LDQSN_1
K18
IO_L45P_A1_M1LDQS_1
K17
IO_L41N_GCLK8_M1CASN_1
K16
IO_L44P_A3_M1DQ6_1
J16
IO_L42P_GCLK7_M1UDM_1
L15
IO_L41P_GCLK9_IRDY1_M1RASN_1
K15
IO_L36N_A8_M1BA1_1
H14
IO_L29P_A23_M1A13_1
C17
IO_L29N_A22_M1A14_1
C18
IO_L31P_A19_M1CKE_1
D17
IO_L31N_A18_M1A12_1
D18
IO_L33P_A15_M1A10_1
E16
IO_L33N_A14_M1A4_1
E18
IO_L35N_A10_M1A2_1
F18
IO_L35P_A11_M1A7_1
F17
IO_L1N_A24_VREF_1
F16
IO_L1P_A25_1
F15
IO_L38N_A4_M1CLKN_1
G18
IO_L38P_A5_M1CLK_1
G16
IO_L43N_GCLK4_M1DQ5_1
H18
IO_L43P_GCLK5_M1DQ4_1
H17
IO_L37N_A6_M1A1_1
H16
IO_L37P_A7_M1A0_1
H15
IO_L49N_M1DQ11_1
P18
IO_L49P_M1DQ10_1
P17
IO_L51P_M1DQ12_1
T17
IO_L52P_M1DQ14_1
U17
IO_L48N_M1DQ9_1
N18
IO_L48P_HDC_M1DQ8_1
N17
IO_L50N_M1UDQSN_1
N16
IO_L74P_AWAKE_1
P15
IO_L74N_DOUT_BUSY_1
P16
IO_L47N_LDC_M1DQ1_1
M18
IO_L47P_FWE_B_M1DQ0_1
M16
IO_L50P_M1UDQS_1
N15
IO_L53N_VREF_1
N14
IO_L46N_FOE_B_M1DQ3_1
L18
IO_L46P_FCS_B_M1DQ2_1
L17
IO_L42N_GCLK6_TRDY1_M1LDM_1
L16
IO_L51N_M1DQ13_1
T18
IO_L52N_M1DQ15_1
U18
IO_L30P_A21_M1RESET_1
F14
IO_L30N_A20_M1A11_1
G14
IO_L32P_A17_M1A8_1
H12
IO_L32N_A16_M1A9_1
G13
IO_L34P_A13_M1WE_1
K12
IO_L34N_A12_M1BA2_1
K13
IO_L36P_A9_M1BA0_1
H13
IO_L39P_M1A3_1
J13
IO_L39N_M1ODT_1
K14
IO_L40P_GCLK11_M1A5_1
L12
IO_L40N_GCLK10_M1A6_1
L13
IO_L53P_1
M14
IO_L61P_1
L14
IO_L61N_1
M13
VCCO_1
E17
VCCO_1
G15
VCCO_1
J14
VCCO_1
J17
VCCO_1
M15
VCCO_1
R17
C41
0.1uF
C41
0.1uF
U5-3
XC6SLX9CSG324
U5-3
XC6SLX9CSG324
IO_L62P_D5_2
R3
IO_L65P_INIT_B_2
U3
IO_L63P_2
T4
IO_L49P_D3_2
U5
IO_L48N_RDWR_B_VREF_2
T5
IO_L43N_2
V7
IO_L43P_2
U7
IO_L46N_2
T7
IO_L41N_VREF_2
V8
IO_L41P_2
U8
IO_L31N_GCLK30_D15_2
T8
IO_L30N_GCLK0_USERCCLK_2
V10
IO_L30P_GCLK1_D13_2
U10
IO_L29N_GCLK2_2
T10
IO_L23P_2
U11
IO_L16N_VREF_2
T11
IO_L14N_D12_2
V13
IO_L14P_D11_2
U13
IO_L3N_MOSI_CSI_B_MISO0_2
T13
IO_L12N_D2_MISO3_2
V14
IO_L12P_D1_MISO2_2
T14
IO_L1N_M0_CMPMISO_2
T15
IO_L2N_CMPMOSI_2
V16
IO_L2P_CMPCLK_2
U16
IO_L45N_2
V6
IO_L65N_CSO_B_2
V3
IO_L63N_2
V4
IO_L49N_D4_2
V5
IO_L32N_GCLK28_2
V9
IO_L45P_2
T6
IO_L23N_2
V11
IO_L62N_D6_2
T3
IO_L1P_CCLK_2
R15
IO_L3P_D0_DIN_MISO_MISO1_2
R13
IO_L13P_M1_2
N12
IO_L13N_D10_2
P12
IO_L16P_2
R11
IO_L29P_GCLK3_2
R10
IO_L31P_GCLK31_D14_2
R8
IO_L32P_GCLK29_2
T9
IO_L46P_2
R7
IO_L48P_D7_2
R5
IO_L64P_D8_2
N5
IO_L64N_D9_2
P6
VCCO_2
P9
VCCO_2
R12
VCCO_2
R6
VCCO_2
U14
VCCO_2
U4
VCCO_2
U9
C40
0.1uF
C40
0.1uF
C42
0.1uF
C42
0.1uF
C47
1.0uF
C47
1.0uF