Datasheet

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SN75LVDT1422
SLLS653 – JUNE 2005
TRANSMITTER SWITCHING CHARACTERISTICS (continued)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
0
Output pulse position for bit 0 –0.25 0 0.25
t
1
Output pulse position for bit 1 3.32 3.57 3.82
t
2
Output pulse position for bit 2 6.89 7.14 7.39
t
3
Output pulse position for bit 3 f = 40 MHz, See Figure 12 10.46 10.71 10.96 ns
t
4
Output pulse position for bit 4 14.04 14.29 14.54
t
5
Output pulse position for bit 5 17.61 17.86 18.11
t
6
Output pulse position for bit 6 21.18 21.43 21.68
t
0
Output pulse position for bit 0 –0.20 0 0.20
t
1
Output pulse position for bit 1 2.00 2.20 2.40
t
2
Output pulse position for bit 2 4.20 4.40 4.60
t
3
Output pulse position for bit 3 f = 65 MHz, See Figure 12 6.39 6.59 6.79 ns
t
4
Output pulse position for bit 4 8.59 8.79 8.99
t
5
Output pulse position for bit 5 10.79 10.99 11.19
t
6
Output pulse position for bit 6 12.99 13.19 13.39
t
0
Output pulse position for bit 0 –0.15 0 0.15
t
1
Output pulse position for bit 1 1.53 1.68 1.83
t
2
Output pulse position for bit 2 3.21 3.36 3.51
t
3
Output pulse position for bit 3 f = 85 MHz, See Figure 12 4.89 5.04 5.19 ns
t
4
Output pulse position for bit 4 6.57 6.72 6.87
t
5
Output pulse position for bit 5 8.25 8.40 8.55
t
6
Output pulse position for bit 6 9.93 10.08 10.23
t
0
Output pulse position for bit 0 -0.2 0 0.2
t
1
Output pulse position for bit 1 1.23 1.43 1.63
t
2
Output pulse position for bit 2 2.66 2.86 3.06
t
3
Output pulse position for bit 3 f = 100 MHz, See Figure 12 4.09 4.29 4.49 ns
t
4
Output pulse position for bit 4 5.51 5.71 5.91
t
5
Output pulse position for bit 5 6.94 7.14 7.34
t
6
Output pulse position for bit 6 8.37 8.57 8.77
t
su
TAx/TBx Setup time to CLK IN 1
f = 85 MHz or 100 MHz, See Figure 6 ns
t
h
TAx/TBx Hold time to CLK IN 0.25
f = 10 MHz 1.0 2.98
f = 25 MHz 1.38 3.21
t
pd(TCC)
CLK IN to TCLK ± Propagation delay time See Figure 7 and Figure 8
(2)
ns
f = 85 MHz 1.60 3.78
f = 100 MHz 1.63 3.95
t
jit(C-C)
TCLK± Clock cycle-to-cycle jitter f = 85 MHz or 100 MHz 50 ps
f = 10 MHz
f = 25 MHz
f = 40 MHz 100
Spread Spectrum Clock support; Modu-
SSCG kHz
lation frequency with a linear profile
(3)
f = 65 MHz ± 2.5%/–5%
f = 85 MHz
f = 100 MHz
t
en(TPLL)
Phase lock loop enable time See Figure 9 10 ms
t
dis(T)
Transmitter disable time See Figure 11 100 ns
(2) Measure from CLK IN rising edge or falling edge to immediately crossing point of differential TCLK ± , 50% duty cycle input clock is
assumed.
(3) Care must be taken to ensure t
su
and t
h
are met so input data are sampling correctly. This SSCG parameter only shows the
performance of tracking spread spectrum clock applied to CLK IN pin, and reflects the result on TCLK+ and TCLK– pins.
8