Datasheet

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SN75LVDT1422
SLLS653 – JUNE 2005
TERMINAL FUNCTIONS
TERMINAL
TYPE DESCRIPTION
NAME NO.
CLK IN 17 LVTTL Input CMOS/LVTTL Clock input
CLK OUT 61 LVTTL Output LVTTL Clock output
Input clock triggering edge select.
R/F 37 LVTTL Input High: Rising edge
Low: Falling edge
RA+, RA– 57, 56 LVDS Input LVDS Data inputs
62, 63, 64, 2,
RA[0:6] LVTTL Output Single-ended data outputs
3, 4, 5
RB+, RB– 53, 52 LVDS Input LVDS Data inputs
8, 9, 10, 11,
RB[0:6] LVTTL Output Single-ended data outputs
13, 14, 15
RCLK+, RCLK– 55, 54 LVDS Input LVDS Clock inputs
Receiver enable: When asserted (low input), the receiver outputs go to a known
RX ENABLE 59 LVTTL Input
low state.
RX GND 6, 16, 60 Ground pins for RX TTL outputs
RX LVDS GND 51 Ground pin for RX LVDS inputs
RX LVDS V
CC
58 Power supply pin for RX LVDS inputs
Power Supply
RX PLL GND 50 Ground pin for PLL RX circuitry
RX PLL V
CC
49 Power supply pin for PLL RX circuitry
RX V
CC
1, 7, 12 Power supply pins for RX TTL outputs
TA+, TA– 41, 42 LVDS Output LVDS Data outputs
19, 20, 21, 23, 24,
TA[0:6] LVTTL Input Single-ended data inputs
25, 26
TB+, TB– 45, 46 LVDS Output LVDS Data outputs
28, 29, 30, 31,
TB[0:6] LVTTL Input Single-ended data inputs
33,34, 35
TCLK+, TCLK– 43, 44 LVDS Output LVDS Clock outputs
Transmitter enable: When asserted (low input), the driver outputs are
TX ENABLE 48 LVTTL Input
high-impedance.
TX GND 18, 36 Ground pins for TX TTL inputs
TX LVDS GND 40 Ground pin for TX LVDS outputs
TX LVDS V
CC
47 Power supply pin for TX LVDS outputs
Power Supply
TX PLL GND 39 Ground pin for PLL TX circuitry
TX PLL V
CC
38 Power supply pin for PLL TX circuitry
TX V
CC
22, 27, 32 Power supply pins for TX TTL inputs
ORDERING INFORMATION
(1)
PRODUCT PACKAGE ORDERING NUMBER
SN75LVDT1422 TQFP (PAG) SN75LVDT1422
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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