Datasheet

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APPLICATION INFORMATION
Power Source Sequence
Transmitter/Receiver Clock/Data Sequencing
Spread Spectrum Clock Support
Receiver Failsafe Feature
Transmitter Input, Receiver Output Pins
SN75LVDT1422
SLLS653 – JUNE 2005
There is no power-on sequence restriction to V
CC
, LVDS V
CC
, and PLL V
CC
. In most applications, it is
recommended to apply the same power source with the separate power planes and decoupling bypass capacitor
groups. Use inductors to connect the different power planes.
There is no special requirement to the sequence of the input clock/data and enable signals. The input clock/data
can be inserted after the enable signal is active. It is not necessary to cycle the enable signal when the
clock/data is stopped and reapplied, like with the case of changing video modes within a graphics controller.
When TX ENABLE pin is pulled low, the LVDS outputs of a SN75LVDT1422 transmitter are high-impedance, the
PLL is shut down, and the transmitter is reset. When RX ENABLE is pulled low, the single-ended outputs of a
SN75LVDT1422 receiver are at low status, the PLL is shut down, and the receiver is reset.
The transmitter of the SN75LVDT1422 accepts spread spectrum clocking signal type inputs. The outputs
accurately track spread spectrum clock/data inputs with modulation frequencies of up to 100 kHz (max) with
either center spread of ±2.5% or down spread -5% deviations.
The receiver input failsafe bias circuitry ensures a stable output with known status while the receiver inputs are
left floating.
When the receiver enable pin is active and a valid clock signal appears at the clock input, all of the data outputs
are high if the data inputs are floating or idle. When the receiver enable pin is active and the clock input is
floating, the last valid state is maintained on the data channels if the inputs are floating or idle. When the receiver
enable pin is inactive, both data and clock outputs are kept low without considering the input status.
In an application with an unused data input, it is recommended to leave it open.
Receiver Failsafe Summary
FAILSAFE RESULT
RX ENABLE DATA CHANNEL STATUS CLOCK CHANNEL STATUS
DATA CLOCK
High Floating/Idle Valid clock signal High Clock
High Floating/Idle Floating/Idle Last state Low
Low Don't Care Don't Care Low Low
The single-ended I/O pins and control input pins are compatible with LVCMOS and LVTTL levels only. These
pins are not 5-V tolerant.
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