Datasheet

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CLK IN
t
c(CLK)
2 V 2 V 2 V
t
wH(CLK)
t
wL(CLK)
0.8 V
V
CC
/2
t
su
t
h
V
CC
/2 Setup Hold V
CC
/2
TA/TB [0:6]
t
pd(TCC)
V
CC
/2
TCLK−
TCLK+
CLK IN
t
pd(TCC)
V
CC
/2
TCLK−
TCLK+
CLK IN
TX ENABLE
CLK IN
INDETERMINATE
V
CC
/2
t
en(TPLL)
TCLK 
SN75LVDT1422
SLLS653 – JUNE 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. Transmitter Setup/Hold and High/Low Times (Falling Edge Strobe)
Figure 7. Transmitter Clock In to Clock Out Propagation Delay Time with R/F at V
CC
Figure 8. Transmitter Clock In to Clock Out Propagation Delay Time with R/F at GND
Figure 9. Transmitter Phase Lock Loop Enable Time
11