Datasheet

www.ti.com
PARAMETER MEASUREMENT INFORMATION
CLK IN / CLK OUT
ODD TA/TB
ODD RA/RB
EVEN TA/TB
EVEN RA/RB
t
5 pF
100 
TA/TB +
TA/TB −
t
r
t
f
80 %
20 %
80 %
20 %
CMOS/TTL output
8 pF
t
r
t
f
80%
20%
80%
20%
Differential
t
t(CLK)
80%
20%
80%
20%
3 V
0 V
t
t(CLK)
CLK IN
SN75LVDT1422
SLLS653 – JUNE 2005
Figure 1. Worst Case Test Pattern
Figure 2. LVDS Output Load
Figure 3. Receiver CMOS/LVTTL Output Load and Transition Times
Figure 4. Transmitter LVDS Transition Times
Figure 5. Transmitter Input Clock Transition Time
10