Datasheet
SLLS268D − MARCH 1997 − REVISED JULY 2006
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
V
IT+
Positive-going differential input threshold voltage 100 mV
V
IT−
Negative-going differential input threshold voltage
‡
−100 mV
V
OH
High-level output voltage I
OH
= −4 mA 2.4 V
V
OL
Low-level output voltage I
OL
= 4 mA 0.4 V
Disabled, All inputs open 280 µA
Enabled,
AnM = 1.4 V,
AnP = 1 V,
t
c
= 15.38 ns
58 72
I
CC
Quiescent current (average)
Enabled,
C
L
= 8 pF,
Grayscale pattern (see Figure 4),
t
c
= 15.38 ns
69
mA
Enabled,
C
L
= 8 pF,
Worst-case pattern (see Figure 5),
t
c
= 15.38 ns
94
I
IH
High-level input current (SHTDN) V
IH
= V
CC
±20 µA
I
IL
Low-level input current (SHTDN) V
IL
= 0 V ±20 µA
I
I
Input current (LVDS input terminals A and CLKIN) 0 ≤ V
I
≤ 2.4 V ±20 µA
I
OZ
High-impedance output current V
O
= 0 or V
CC
±10 µA
†
All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
‡
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going
input voltage threshold only.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
t
su2
Set up time, D0−D20 valid to CLKOUT↓ C
L
= 8 pF, See Figure 6 5 ns
t
h2
Hold time, CLKOUT↓ to D0−D20 valid C
L
= 8 pF, See Figure 6 5 ns
t
RSKM
Receiver input skew margin
§
(see Figure 7)
t
c
= 15.38 ns (±0.2%),
|Input clock jitter| < 50 ps
¶
490 ps
t
d
Delay time, CLKIN↑ to CLKOUT↓
(see Figure 7)
t
c
= 15.38 ns (±0.2%), C
L
= 8 pF 3.7 ns
∆
t
c(o)
Cycle time, change in output clock period
#
t
c
= 15.38 + 0.75 sin (2π500E3t) ± 0.05
ns,
See Figure 8
±80
ps
∆t
c(o)
Cycle time, change in output clock period
#
t
c
= 15.38 + 0.75 sin (2π3E6t) ± 0.05 ns,
See Figure 8
±300
ps
t
en
Enable time, SHTDN↑ to Dn valid
See Figure 9 1 ms
t
dis
Disable time, SHTDN↓ to off state
See Figure 10 400 ns
t
t
Transition time, output (10% to 90% t
r
or t
f
) C
L
= 8 pF 3 ns
t
w
Pulse duration, output clock 0.43 t
c
ns
†
All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
§
The parameter t
(RSKM)
is the timing margin available to the transmitter and interconnection skews and clock jitter. It is defined by
t
c
14
* t
su1
ńt
h1
.
¶
|Input clock jitter| is the magnitude of the change in input clock period.
#
∆t
c(o)
is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.