Datasheet


 
SLLS268D − MARCH 1997 − REVISED JULY 2006
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
The LVDS receivers of the SN75LVDS86 include an open-circuit fail-safe design, such that when the inputs are
not connected to an LVDS driver, the receiver outputs go to a low level. This occurs even when the line is
differentially terminated at the receiver inputs.
The SN75LVDS86 is characterized for operation over ambient free-air temperatures of 0_C to 70_C.
functional block diagram
Serial In
CLK
Serial-In/Parallel-
Out Shift Register
Serial In
CLK
Serial In
CLK
Control Logic
CLK
Clock In
7× Clock/PLL
SHTDN
CLKINP
A2P
A2M
A1P
A1M
A0P
A0M
CLKOUT
CLKINM
D14
D15
D16
D17
D18
D19
D20
D7
D8
D9
D10
D11
D12
D13
D0
D1
D2
D3
D4
D5
D6
A, B, ...G
Clock Out
A, B, ...G
A, B, ...G
Serial-In/Parallel-
Out Shift Register
Serial-In/Parallel-
Out Shift Register
Input Bus