Datasheet

SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements
MIN NOM MAX UNIT
t
c
Input clock period 13.3 t
c
32.4 ns
t
w
Pulse duration, high-level input clock 0.4t
c
0.6t
c
ns
t
t
Transition time, input signal 5 ns
t
su
Setup time, data, D0 – D20 valid before CLKIN↓ (see Figure 2) 3 ns
t
h
Hold time, data, D0 – D20 valid after CLKIN↓ (see Figure 2) 1.5 ns
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
V
IT
Input threshold voltage 1.4 V
|V
OD
|
Differential steady-state output voltage
magnitude
R
L
= 100 Ω, See Figure 3 247 454 mV
∆|V
OD
|
Change in the steady-state differential output
voltage magnitude between opposite binary
states
50 mV
V
OC(SS)
Steady-state common-mode output voltage R
L
= 100 Ω, See Figure 3 1.125 1.375 V
V
OC(PP)
Peak-to-peak common-mode output voltage 80 150 mV
I
IH
High level in
p
ut current
V
IH
=V
CC
SN75LVDS84A 20
µA
I
IH
High
-
level
input
current
V
IH
=
V
CC
SN65LVDS84AQ 25
µ
A
I
IL
Low-level input current V
IL
= 0 ±10 µA
I
OS
Short circuit out
p
ut current
V
O(Yn)
= 0 –6 ±24 mA
I
OS
Short
-
circuit
output
current
V
OD
= 0 –6 ±12 mA
I
OZ
High-impedance output current V
O
= 0 to V
CC
±10 µA
Disabled,
SN75LVDS84A 15 150
µA
,
All inputs at GND
SN65LVDS84AQ 15 170
µ
A
Enabled,
R
L
= 100 Ω
(
4 places
)
f = 65 MHz 27 35
I
CC(AVG)
Quiescent supply current (average)
L
()
Gray-scale pattern
(see Figure 4)
f = 75 MHz 30 38
mA
Enabled,
R
L
= 100 Ω,
(
4 places
)
f = 65 MHz 28 36
mA
L
,( )
Worst-case pattern
(see Figure 5)
f = 75 MHz 31 39
C
I
Input capacitance 2 pF
†
All typical values are at V
CC
= 3.3 V, T
A
= 25°C.