Datasheet

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SLLS271I − MARCH 1997 − REVISED MAY 2009
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Dn
t
su
CLKIN
t
h
CLKSEL LOW
CLKSEL HIGH
NOTE A: All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns.
Figure 2. Setup and Hold Time Waveforms
C
L
= 10 pF Max
(2 Places)
49.9 Ω ± 1% (2 Places)
V
OC
V
OD
YP
YM
V
OD(H)
V
OC(SS)
V
OC(SS)
V
OD(L)
100%
80%
20%
0%
0 V
V
OC(PP)
t
r
t
f
0 V
(a) SCHEMATIC
(b) WAVEFORMS
NOTE A: The lumped instrumentation capacitance for any
single-ended voltage measurement is less than or equal
to 10 pF. When making measurements at YP or YM, the
complementary output is similarly loaded.
Figure 3. Test Load and Voltage Waveforms for LVDS Outputs
Not Recommended for New Designs