Datasheet

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 
SLLS271I − MARCH 1997 − REVISED MAY 2009
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
t
d0
Delay time, CLKOUT↑ to serial bit position 0 −0.2 0 0.2 ns
t
d1
Delay time, CLKOUT↑ to serial bit position 1
1
7
t
c
* 0.2
1
7
t
c
) 0.2
ns
t
d2
Delay time, CLKOUT↑ to serial bit position 2
2
7
t
c
* 0.2
2
7
t
c
) 0.2
ns
t
d3
Delay time, CLKOUT↑ to serial bit position 3
t
c
= 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps
‡
, See Figure 6
3
7
t
c
* 0.2
3
7
t
c
) 0.2
ns
t
d4
Delay time, CLKOUT↑ to serial bit position 4
c
|Input clock jitter| < 50 ps
‡
, See Figure 6
4
7
t
c
* 0.2
4
7
t
c
) 0.2
ns
t
d5
Delay time, CLKOUT↑ to serial bit position 5
5
7
t
c
* 0.2
5
7
t
c
) 0.2
ns
t
d6
Delay time, CLKOUT↑ to serial bit position 6
6
7
t
c
* 0.2
6
7
t
c
) 0.2
ns
t
sk(o)
Output skew,
t
n
*
n
7
t
c
−0.2 0.2 ns
t
d7
Delay time, CLKIN↓ to CLKOUT↑
t
c
= 18.51 ns (± 0.2%),
|Input clock jitter| < 50 ps
‡
, See Figure 6
3.75 5.6 7.75 ns
∆t
c(o)
Cycle time, output clock jitter
§
t
c
= 15.38 ± 0.75 sin (2π500E3t) + 0.05 ns,
See Figure 7
±70 ps
∆t
c(o
)
Cycle time, output clock jitter
§
t
c
= 15.38 ± 0.75 sin (2π3E6t) + 0.05 ns,
See Figure 7
±187 ps
t
w
Pulse duration, high-level output clock
4
7
t
c
ns
t
t
Transition time, differential output (t
r
or t
f
) See Figure 3 260 700 1500 ps
t
en
Enable time, SHTDN↑ to phase lock (Yn
valid)
See Figure 8 1 ms
t
dis
Disable time, SHTDN↓ to off state
(CLKOUT low)
See Figure 9 250 ns
†
All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
‡
|Input clock jitter| is the magnitude of the change in the input clock period.
§
Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.
Not Recommended for New Designs