Datasheet

SN75LVDS83B

SLLS846B –MAY 2009–REVISED SEPTEMBER 2011

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ZQL PIN LIST (continued)

K1 D1 K2 D2 K3 D4

K4 D5 K5 D7 K6 D8

PIN FUNCTIONS

TERMINAL I/O DESCRIPTION

Y0P, Y0M, Y1P, Differential LVDS data outputs.

Y1M, Y2P, Y2M Outputs are high-impedance when SHTDN is pulled low (de-asserted)

Differential LVDS Data outputs.

Y3P, Y3M LVDS Out Output is high-impedance when SHTDN is pulled low (de-asserted).

Note: if the application only requires 18-bit color, this output can be left open.

Differential LVDS pixel clock output.

CLKP, CLKM

Output is high-impedance when SHTDN is pulled low (de-asserted).

Data inputs; supports 1.8V to 3.3V input voltage selectable by VDD supply. To connect a graphic

source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily

intuitive).

D0 – D27

For input bit assignment see Figure 14 to Figure 17 for details.

Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23,

and D27 to GND.

CMOS IN with

pulldn

CLKIN Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.

Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and

SHTDN

high (assert) for normal operation.

Selects between rising edge input clock trigger (CLKSEL = V

) and falling edge input clock trigger

CLKSEL

(CLKSEL = V

VCC 3.3V digital supply voltage

IOVCC I/O supply reference voltage (1.8V up to 3.3V matching the GPU data output signal swing)

PLLVCC Power Supply

(1)

3.3V PLL analog supply

LVDSVCC 3.3V LVDS output analog supply

GND Supply ground for VCC, IOVCC, LVDSVCC, and PLLVCC.

(1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals

directly to this plane.