Datasheet

SN75LVDS83B18-bpp GPU
R0(LSB)
R1
R2
R3
R4
R5(MSB)
G0(LSB)
G1
G2
G3
G4
G5(MSB)
B0(LSB)
B1
B2
B3
B4
B5(MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
CLKOUTM
CLKOUTP
(See Note A)
(See Note B)
Y3M
Y3P
FPC
Cable
VDD
GPU
IO
1.8V or 2.5V
or 3.3V
GND IOVCC CLKSEL
Rpullup
Rpulldown
VCC LVDSVCC
PLLVCC GND
3.3V
C2C1 C3
3.3V
100
LVDS
timing
Controller
(6-bpc, 18-bpp)
100
100
100
to column
driver
to row driver
Main Board
SHTDN
4.8k
18-bpp LCD Display
Panel connector
Main board connector
SN75LVDS83B
www.ti.com SLLS846B –MAY 2009–REVISED SEPTEMBER 2011
Note A. Leave output Y3 NC.
Note B.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
• C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
• C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
• C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 15. 18-Bit Color Host to 18-Bit Color LCD Panel Display Application
Copyright © 2009–2011, Texas Instruments Incorporated 17