Datasheet

SN75LVDS83B

www.ti.com

SLLS846B –MAY 2009–REVISED SEPTEMBER 2011

APPLICATION INFORMATION

This section describes the power up sequence, provides information on device connectivity to various GPU and

LCD display panels, and offers a pcb routing example.

Power Up Sequence

The SN75LVDS83B does not require a specific power up sequence.

It is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to

GND. The input level of the SHTDN during this time does not matter as only the input stage is powered up while

all other device blocks are still powered down.

It is also permitted to power up all 3.3V power domains while IOVCC is still powered down to GND. The device

will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of their true

input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic HIGH; the LVDS output

stage will turn on. The power consumption in this condition is significantly higher than standby mode, but still

lower than normal mode.

The user experience can be impacted by the way a system powers up and powers down an LCD screen. The

following sequence is recommended:

Power up sequence (SN75LVDS83B SHTDN input initially low):

1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.

2. Wait for additional 0-200ms to ensure display noise won’t occur.

3. Enable video source output; start sending black video data.

4. Toggle LVDS83B shutdown to SHTDN = V

5. Send >1ms of black video data; this allows the LVDS83B to be phase locked, and the display to show black

data first.

6. Start sending true image data.

7. Enable backlight.

Power Down sequence (SN75LVDS83B SHTDN input initially high):

1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.

2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive

this for >2 frame times.

3. Set SN75LVDS83B input SHTDN = GND; wait for 250ns.

4. Disable the video output of the video source.

5. Remove power from the LCD panel for lowest system power.

Signal Connectivity

While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the

industry has aligned over the years on a certain data format (bit order). Figure 14 through Figure 17 show how

each signal should be connected from the graphic source through the SN75LVDS83B input, output and LVDS

LCD panel input. Detailed notes are provided with each figure.