Datasheet

SN75LVDS83B
SLLS846B –MAY 2009–REVISED SEPTEMBER 2011 www.ti.com
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Delay time, CLKOUT↑ after Yn valid
t
0
(serial bit position 0, equal D1, D9, -0.1 0 0.1 ns
D20, D5)
Delay time, CLKOUT↑ after Yn valid
t
1
(serial bit position 1, equal D0, D8,
1
/
7
t
c
- 0.1
1
/
7
t
c
+ 0.1 ns
D19, D27)
Delay time, CLKOUT↑ after Yn valid
t
2
(serial bit position 2, equal D7, D18,
2
/
7
t
c
- 0.1
2
/
7
t
c
+ 0.1 ns
D26. D23)
Delay time, CLKOUT↑ after Yn valid
See Figure 7, t
C
= 10ns,
t
3
(serial bit position 3; equal D6, D15,
3
/
7
t
c
- 0.1
3
/
7
t
c
+ 0.1 ns
|Input clock jitter| < 25ps
(2)
D25, D17)
Delay time, CLKOUT↑ after Yn valid
t
4
(serial bit position 4, equal D4, D14,
4
/
7
t
c
- 0.1
4
/
7
t
c
+ 0.1 ns
D24, D16)
Delay time, CLKOUT↑ after Yn valid
t
5
(serial bit position 5, equal D3, D13,
5
/
7
t
c
- 0.1
5
/
7
t
c
+ 0.1 ns
D22, D11)
Delay time, CLKOUT↑ after Yn valid
t
6
(serial bit position 6, equal D2, D12,
6
/
7
t
c
- 0.1
6
/
7
t
c
+ 0.1 ns
D21, D10)
t
c(o)
Output clock period t
c
ns
t
C
= 10ns; clean reference clock, see
±26
Figure 8
t
C
= 10ns with 0.05UI added noise
±44
modulated at 3MHz, see Figure 8
Δt
c(o)
Output clock cycle-to-cycle jitter
(3)
ps
t
C
= 7.4ns; clean reference clock,
±35
see Figure 8
t
C
= 7.4ns with 0.05UI added noise
±42
modulated at 3MHz, see Figure 8
High-level output clock pulse
t
w
4
/
7
t
c
ns
duration
Differential output voltage transition
t
r/f
See Figure 4 225 500 ps
time (t
r
or t
f
)
Enable time, SHTDN↑ to phase lock
t
en
f
(clk)
= 135MHz, See Figure 9 6 µs
(Yn valid)
Disable time, SHTDN↓ to off-state
t
dis
f
(clk)
= 135MHz, See Figure 10 7 ns
(CLKOUT high-impedance)
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed
over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.
THERMAL CHARACTERISTICS
ZQL DGG
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
Low-K JEDEC test board, 1s (single signal layer), no air flow 85
Junction-to-free-air
θ
JA
°C/W
High-K JEDEC test board, 2s2p (double signal layer, double
thermal resistance
67.1 63.4
buried power plane), no air flow
Junction-to-case
θ
JC
Cu cold plate measurement process 25.2 15.9 °C/W
thermal resistance
Junction-to-board
θ
JB
EIA/JESD 51-8 31.0 32.5 °C/W
thermal resistance
Junction-to-top of
ψ
JT
EIA/JESD 51-2 0.8 0.4 °C/W
package
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