Datasheet

SN75LVDS83A

www.ti.com

SLLS980D –JUNE 2009– REVISED JUNE 2011

PIN FUNCTIONS

TERMINAL I/O DESCRIPTION

Y0P, Y0M, Y1P, Differential LVDS data outputs.

Y1M, Y2P, Y2M Outputs are high-impedance when SHTDN is pulled low (de-asserted)

Differential LVDS Data outputs.

Y3P, Y3M LVDS Out Output is high-impedance when SHTDN is pulled low (de-asserted).

Note: if the application only requires 18-bit color, this output can be left open.

Differential LVDS pixel clock output.

CLKP, CLKM

Output is high-impedance when SHTDN is pulled low (de-asserted).

Data inputs. To connect a graphic source successfully to a display, the bit assignment of D[27:0] is

critical (and not necessarily intuitive).

D0 – D27 For input bit assignment see Figure 14 to Figure 17 for details.

Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23,

and D27 to GND.

CMOS IN with

CLKIN Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.

pulldn

Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and

SHTDN

high (assert) for normal operation.

Selects between rising edge input clock trigger (CLKSEL = V

) and falling edge input clock trigger

CLKSEL

(CLKSEL = V

VCC 3.3V digital Supply Voltage

PLLVCC 3.3V PLL analog supply

Power Supply

(1)

LVDSVCC 3.3V LVDS output analog supply

GND Supply Ground for VCC, LVDSVCC, and PLLVCC.

(1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals

directly to this plane.