Datasheet

SN75LVDS83A18-bpp GPU
R0(LSB)
R1
R2
R3
R4
R5(MSB)
G0(LSB)
G1
G2
G3
G4
G5(MSB)
B0(LSB)
B1
B2
B3
B4
B5(MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
CLKOUTM
CLKOUTP
Y3M
Y3P
FPC
Cable
100
LVDS
timing
Controller
(6-bpc,
18-bpp)
Panel connector
100
100
100
Main board connector
to column
driver
to row driver
18-bpp LCD Display
GND VCC CLKSEL VCC LVDSVCC PLLVCC GND SHTDN
3.3V
Rpullup
Rpulldow
3.3V
C1* C2*
3.3V
4.8k
(See Note B)
(See Note A)
Main Board
SN75LVDS83A
SLLS980D –JUNE 2009–REVISED JUNE 2011 www.ti.com
Note A. Leave output Y3 NC.
Note B.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
• C1: decoupling cap for the VDDIO supply; install at least 1 × 0.1μF and 1 × 0.01μF.
• C2: decoupling cap for the VDD supply; install at least 1 × 0.1μF and 1 × 0.01μF.
Figure 15. 18-Bit Color Host to 18-Bit Color LCD Panel Display Application
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