Datasheet

SN75LVDS83A24-bpc GPU
R0(LSB)
R1
R2
R3
R4
R5
R6
R7(MSB)
G0(LSB)
G1
G2
G3
G4
G5
G6
G7(MSB)
B0(LSB)
B1
B2
B3
B4
B5
B6
B7(MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
FORMAT1
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
Y3M
Y3P
CLKOUTM
CLKOUTP
FPC
Cable
3.3V
GND
100
LVDS
timing
Controller
(8bpc,
24bpp)
Panel connector
100
100
100
100
Main board connector
to column
driver
to row driver
Main Board
CLKSEL
Rpullup
Rpulldown
VCC LVDSVCC PLLVCC GND
3.3V
C1* C2*
3.3V
SHTDN
4.8k
24-bpp LCD Display
FORMAT2
D27
D5
D0
D1
D2
D3
D4
D6
D10
D11
D7
D8
D9
D12
D13
D14
D16
D17
D15
D18
D19
D20
D21
D22
D24
D25
D26
D23
CLKIN
(See Note B)
(See Note A)
SN75LVDS83A
www.ti.com SLLS980D –JUNE 2009– REVISED JUNE 2011
Note A. FORMAT: The majority of 24-bit LCD display panels require the two LSBs of each color to be transferred
over the 4th serial data output Y3. Other 24-bit LCD display panels require the two LSB of each color to be
transmitted over the Y3 output. The system designer needs to verify which format is expected by checking the LCD
display data sheet.
• Format 1: use with displays expecting the 2 MSB to be transmitted over the 4th data channel Y3. This is the
dominant data format in today's LCD panels
• Format 2: use with displays expecting the 2 LSB to be transmitted over the 4th data channel.
Note B. Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
• C1: decoupling cap for the VDDIO supply; install at least 1 × 0.1μF and 1 × 0.01μF
• C2: decoupling cap for the VDD supply; install at least 1 × 0.1μF and 1 × 0.01μF.
Figure 14. 24-Bit Color Host to 24-bit LCD Panel Application
Copyright © 2009–2011, Texas Instruments Incorporated 15