Datasheet
tsu
thold
Dn
CLKIN
V
OD
49.9 ±1%(2PLCS)W
YP
YM
t
f
t
r
0%
20%
80%
100%
0V
0V
V
OC
V
OD(H)
V
OC(SS)
V
OD(L)
V
OC(SS)
V
OC(PP)
CLKIN
D0,8,16
D1,9,17
D2,10,18
D3,11,19
D4-7,12-15,20-23
D24-27
SN75LVDS83A
SLLS980D –JUNE 2009–REVISED JUNE 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns.
CLKSEL = 0V.
Figure 3. Set Up and Hold Time Definition
Figure 4. Test Load and Voltage Definitions for LVDS Outputs.
The 16 grayscale test pattern test device power consumption for a typical display pattern.
Figure 5. 16 Grayscale Test Pattern
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