Datasheet

SN75LVDS82
www.ti.com SLLS259I –NOVEMBER 1996– REVISED APRIL 2011
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT+
Positive-going differential input threshold voltage 100 mV
V
IT–
Negative-going differential input threshold voltage
(2)
–100 mV
V
OH
High-level output voltage I
OH
= –4 mA 2.4 V
V
OL
Low-level output voltage I
OL
= 4 mA 0.4 V
Disabled, All inputs open 280 μA
Enabled, AnP = 1 V,
AnM = 1.4 V, 60 74
t
c
= 15.38 ns
Enabled, C
L
= 8 pF,
Grayscale pattern
I
CC
Quiescent current (average)
74
(see Figure 4), mA
t
c
= 15.38 ns
Enabled, C
L
= 8 pF,
Worst-case pattern
107
(see Figure 5),
t
c
= 15.38 ns
I
IH
High-level input current (SHTDN) V
IH
= V
CC
±20 μA
I
IL
Low-level input current (SHTDN) V
IL
= 0 ±20 μA
I
IN
Input current (LVDS input terminals A and CLKIN) 0 ≤ V
I
≤ 2.4 V ±20 μA
I
OZ
High-impedance output current V
O
= 0 or V
CC
±10 μA
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
(2) The algebraic convention, in which the less-positive (more-negative) limit is designed minimum, is used in this data sheet for the
negative-going input voltage threshold only.
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
su2
Setup time, D0–D27 valid to CLKOUT↓ C
L
= 8 pF, See Figure 6 5 ns
t
h2
Hold time, CLKOUT↓ to D0–D27 valid C
L
= 8 pF, See Figure 6 5 ns
t
c
= 15.38 ns (± 0.2%),
t
RSKM
Receiver input skew margin
(2)
(see Figure 7) 490 ps
|Input clock jitter| < 50 ps
(3)
t
d
Delay time, CLKIN↑ to CLKOUT↓ (see Figure 7) t
c
= 15.38 ns (± 0.2%), C
L
= 8 pF 3.7 ns
t
c
= 15.38 + 0.75 sin (2π500E3t) ± 0.05 ns,
±80
See Figure 8
Δt
c(o)
Cycle time, change in output clock period
(4)
ps
t
c
= 15.38 + 0.75 sin (2π3E6t) ± 0.05 ns,
±300
See Figure 8
t
en
Enable time, SHTDN↑ to Dn valid See Figure 9 1 ms
t
dis
Disable time, SHTDN↓ to off state See Figure 10 400 ns
t
t
Transition time, output (10% to 90% t
r
or t
f
) C
L
= 8 pF 3 ns
t
w
Pulse duration, output clock 0.43 t
c
ns
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
(2) The parameter t
(RSKM)
is the timing margin available to the transmitter and interconnection skews and clock jitter. It is defined by
t
c
/14 – t
su1
/t
h1
.
(3) |Input clock jitter| is the magnitude of the change in input clock period.
(4) Δt
c(o)
is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.
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