Datasheet

Serial In
CLK
Serial-In/Parallel-
Out Shift Register
Serial In
CLK
Serial In
CLK
Serial In
CLK
Control Logic
7× CLK
Clock In
7× Clock/PLL
SHTDN
CLKINP
A4P
A4M
A3P
A3M
A2P
A2M
A1P
A1M
CLKOUT
CLKINM
D27
D5
D10
D11
D16
D17
D23
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
D0
D1
D2
D3
D4
D6
D7
A, B, ...G
Clock Out
A, B, ...G
A, B, ...G
A, B, ...G
Serial-In/Parallel-
Out Shift Register
Serial-In/Parallel-
Out Shift Register
Serial-In/Parallel-
Out Shift Register
Input Bus
SN75LVDS82
SLLS259I –NOVEMBER 1996–REVISED APRIL 2011 www.ti.com
The SN75LVDS82 requires only five line-termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user. The only possible user intervention is the use of the shutdown/clear
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A
low-level on SHTDN clears all internal registers to a low level and places the CMOS outputs in a high-impedance
state.
The SN75LVDS82 is characterized for operation over ambient air temperatures of 0°C to 70°C.
FUNCTIONAL BLOCK DIAGRAM
2 Copyright © 1996–2011, Texas Instruments Incorporated