Datasheet

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SLLS173F − JANUARY 1994 − REVISED APRIL 2006
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
OD
V
test
R1
375
0 V or 3 V
Z
D
R2
375
V
test
Y
R
L
= 60
7 V < V
test
< 12 V
Figure 2. Differential Output Voltage Test Circuit
0 V
3 V
t
t(OD)
t
t(OD)
1.5 V
t
d(ODH)
50%
Output
Input
TEST CIRCUIT VOLTAGE WAVEFORMS
t
d(ODL)
R
L
= 54
Output
Generator
(see Note A)
50
1.5 V
50%
2.5 V
− 2.5 V
C
L
= 50 pF
(see Note B)
1.5 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, t
r
6 ns, t
f
6 ns,
Z
O
=50.
B. C
L
includes probe and jig capacitance.
Figure 3. Driver Test Circuits and Differential Output Delay and Transition Time Voltage Waveforms
TEST CIRCUIT VOLTAGE WAVEFORMS
V
OL
V
OH
3 V
0 V
t
PHL
t
PLH
Output
Input
1.3 V
1.5 V
1.3 V
50
Output
1.5 V
Generator
(see Note A)
A
B
t
t
90%
10%10%
90%
t
t
C
L
= 15 pF
(see Note B)
1.5 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, t
r
6 ns, t
f
6 ns,
Z
O
=50.
B. C
L
includes probe and jig capacitance.
Figure 4. Receiver Test Circuit and Propagation Delay and Transition Time Voltage Waveforms