Datasheet

 
    
SLLS171G − OCTOBER 1993 − REVISED MARCH2009
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
2B
2A
1B
1A
1,2EN
2Y
1Y
5
3
7
6
1
2
4
EN
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
4B
4A
3B
3A
3,4EN
4Y
3Y
13
11
15
14
9
10
12
EN
logic diagram (positive logic)
2Y
1Y
5
3
7
6
1
2
4
2B
2A
1B
1A
1,2EN
4Y
3Y
13
11
15
14
9
10
12
4B
4A
3B
3A
3,4EN
FUNCTION TABLE
(each receiver)
DIFFERENTIAL INPUTS
A−B
ENABLE
OUTPUT
Y
V
ID
≥ 0.2 V H H
−0.2 V < V
ID
< 0.2 V H ?
V
ID
≤ −0.2 V H L
X L Z
Open circuit H H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
V
CC
Y Output
EQUIVALENT OF A AND B INPUTS
12 kΩ
3 kΩ
18 kΩ
1 kΩ
V
CC
Input
100 kΩ
(A Only)
100 kΩ
(B Only)
Input
V
CC
TYPICAL OF EN INPUT
Outpu
t
Receiver